From: Matthew Wahab Date: Tue, 22 Sep 2015 09:30:51 +0000 (+0000) Subject: [AArch64] Add atomic load-operate instructions. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6380d2bc38237e00e3d460882b4b0938bbb068b9;p=gcc.git [AArch64] Add atomic load-operate instructions. 2015-09-22 Matthew Wahab * config/aarch64/aarch64/atomics.md (UNSPECV_ATOMIC_LDOP): New. (UNSPECV_ATOMIC_LDOP_OR): New. (UNSPECV_ATOMIC_LDOP_BIC): New. (UNSPECV_ATOMIC_LDOP_XOR): New. (UNSPECV_ATOMIC_LDOP_PLUS): New. (ATOMIC_LDOP): New. (atomic_ldop): New. (aarch64_atomic_load): New. From-SVN: r228000 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 568d1d758c6..27e773b5e98 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2015-09-22 Matthew Wahab + + * config/aarch64/aarch64/atomics.md (UNSPECV_ATOMIC_LDOP): New. + (UNSPECV_ATOMIC_LDOP_OR): New. + (UNSPECV_ATOMIC_LDOP_BIC): New. + (UNSPECV_ATOMIC_LDOP_XOR): New. + (UNSPECV_ATOMIC_LDOP_PLUS): New. + (ATOMIC_LDOP): New. + (atomic_ldop): New. + (aarch64_atomic_load): New. + 2015-09-22 Matthew Wahab * config/aarch64/aarch64.md diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index cb8053942c8..11a9d1374c8 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -29,8 +29,25 @@ UNSPECV_ATOMIC_CAS ; Represent an atomic CAS. UNSPECV_ATOMIC_SWP ; Represent an atomic SWP. UNSPECV_ATOMIC_OP ; Represent an atomic operation. + UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation + UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or + UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic + UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor + UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add ]) +;; Iterators for load-operate instructions. + +(define_int_iterator ATOMIC_LDOP + [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC + UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS]) + +(define_int_attr atomic_ldop + [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr") + (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")]) + +;; Instruction patterns. + (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "register_operand" "") ;; bool out (match_operand:ALLI 1 "register_operand" "") ;; val out @@ -536,3 +553,27 @@ else return "casal\t%0, %2, %1"; }) + +;; Atomic load-op: Load data, operate, store result, keep data. + +(define_insn "aarch64_atomic_load" + [(set (match_operand:ALLI 0 "register_operand" "=r") + (match_operand:ALLI 1 "aarch64_sync_memory_operand" "+Q")) + (set (match_dup 1) + (unspec_volatile:ALLI + [(match_dup 1) + (match_operand:ALLI 2 "register_operand") + (match_operand:SI 3 "const_int_operand")] + ATOMIC_LDOP))] + "TARGET_LSE && reload_completed" + { + enum memmodel model = memmodel_from_int (INTVAL (operands[3])); + if (is_mm_relaxed (model)) + return "ld\t%2, %0, %1"; + else if (is_mm_acquire (model) || is_mm_consume (model)) + return "lda\t%2, %0, %1"; + else if (is_mm_release (model)) + return "ldl\t%2, %0, %1"; + else + return "ldal\t%2, %0, %1"; + })