From: Oleg Endo <olegendo@gcc.gnu.org>
Date: Wed, 13 Jun 2012 18:45:17 +0000 (+0000)
Subject: re PR target/53568 (SH Target: Add support for bswap built-ins)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=638a085f5c16d6557ffa7f40b73ef80d354ed8bd;p=gcc.git

re PR target/53568 (SH Target: Add support for bswap built-ins)

	PR target/53568
	* config/sh/sh.md (bswapsi2): New expander.
	(swapbsi2): New insn.

From-SVN: r188524
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 43e53235a53..41a3e07a953 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2012-06-13  Oleg Endo  <olegendo@gcc.gnu.org>
+
+	PR target/53568
+	* config/sh/sh.md (bswapsi2): New expander.
+	(swapbsi2): New insn.
+
 2012-06-13  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/53647
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index eaf099ec6c9..05a4f38c1dc 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -4529,6 +4529,38 @@ label:
   emit_label_after (skip_neg_label, emit_insn (gen_negc (high_dst, high_src)));
   DONE;
 })
+
+(define_expand "bswapsi2"
+  [(set (match_operand:SI 0 "arith_reg_dest" "")
+	(bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
+  "TARGET_SH1"
+{
+  if (! can_create_pseudo_p ())
+    FAIL;
+  else
+    {
+      rtx tmp0 = gen_reg_rtx (SImode);
+      rtx tmp1 = gen_reg_rtx (SImode);
+
+      emit_insn (gen_swapbsi2 (tmp0, operands[1]));
+      emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
+      emit_insn (gen_swapbsi2 (operands[0], tmp1));
+      DONE;
+    }
+})
+
+(define_insn "swapbsi2"
+  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
+	(ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
+			(const_int 4294901760))
+		(ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
+				(const_int 65280))
+			(and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
+				(const_int 255)))))]
+  "TARGET_SH1"
+  "swap.b	%1,%0"
+  [(set_attr "type" "arith")])
+
 
 ;; -------------------------------------------------------------------------
 ;; Zero extension instructions