From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Jun 2020 11:44:23 +0000 (+0100)
Subject: add a test SRAM that lives behind a minerva LoadStoreUnitInterface
X-Git-Tag: div_pipeline~267
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=638a80fc060668f0cb4a5310534e2c950a2f2426;p=soc.git

add a test SRAM that lives behind a minerva LoadStoreUnitInterface
---

diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py
new file mode 100644
index 00000000..e009c62a
--- /dev/null
+++ b/src/soc/bus/test/test_minerva.py
@@ -0,0 +1,26 @@
+from nmigen_soc.wishbone.sram import SRAM
+from nmigen import Memory, Signal, Module
+from soc.minerva.units.loadstore import BareLoadStoreUnit, CacheLoadStoreUnit
+
+
+class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit):
+    def __init__(self, addr_wid=64, mask_wid=4, data_wid=64):
+        super().__init__(addr_wid, mask_wid, data_wid)
+
+    def elaborate(self, platform):
+        m = Module()
+        comb = m.d.comb
+        m.submodules.mem = memory = Memory(width=addr_wid, depth=16)
+        m.submodules.sram = sram = SRAM(memory=memory, granularity=8,
+                                        features=set('cti', 'bte', 'err'))
+        dbus = self.dbus
+
+        # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
+        # note: SRAM is a target (slave), dbus is initiator (master)
+        fanouts = ['adr', 'dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
+        fanins = ['dat_r', 'ack', 'err']
+        for fanout in fanouts:
+            comb += getattr(sram.bus, fanout).eq(getattr(dbus))
+        for fanin in fanins:
+            comb += getattr(dbus, fanin).eq(getattr(sram.bus))
+
diff --git a/src/soc/config/loadstore.py b/src/soc/config/loadstore.py
index 8291276a..37e2bf38 100644
--- a/src/soc/config/loadstore.py
+++ b/src/soc/config/loadstore.py
@@ -4,17 +4,17 @@ allows the type of LoadStoreUnit to be run-time selectable
 
 """
 from soc.experiment.pimem import TestMemoryLoadStoreUnit
-from soc.minerva.units.loadstore import BareLoadStoreUnit, CacheLoadStoreUnit
+from soc.bus.test.test_minerva import TestSRAMBareLoadStoreUnit
 
 
 class ConfigureableLoadStoreUnit:
     def __init__(self, pspec):
         lsidict = {'testmem': TestMemoryLoadStoreUnit,
-                   'bare_wb': BareLoadStoreUnit,
-                   'cache_wb': CacheLoadStoreUnit # TODO dcache parameters
+                   'test_bare_wb': TestBareLoadStoreUnit,
+                   #'test_cache_wb': TestCacheLoadStoreUnit
                   }
         lsikls = lsidict[pspec.ldst_ifacetype]
-        self.lsi = lsikls(addr_wid=pspec.addr_wid,
+        self.lsi = lsikls(addr_wid=pspec.addr_wid, # address range
                           mask_wid=pspec.mask_wid, # cache line range
-                          data_wid=pspec.reg_wid)
+                          data_wid=pspec.reg_wid)  # data bus width