From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 9 May 2020 14:04:55 +0000 (+0100)
Subject: TODO on AluIntermediateData
X-Git-Tag: div_pipeline~1317
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6396eac49bb617c605fa61b87ae68f951fed1c5c;p=soc.git

TODO on AluIntermediateData
---

diff --git a/src/soc/alu/pipe_data.py b/src/soc/alu/pipe_data.py
index 083ca105..d512dc01 100644
--- a/src/soc/alu/pipe_data.py
+++ b/src/soc/alu/pipe_data.py
@@ -38,6 +38,10 @@ class ALUInputData(IntegerData):
                       self.carry_in.eq(i.carry_in),
                       self.so.eq(i.so)]
 
+# TODO: ALUIntermediateData which does not have
+# cr0, ov, ov32 in it (because they are generated as outputs by
+# the final output stage, not by the intermediate stage)
+# https://bugs.libre-soc.org/show_bug.cgi?id=305#c19
 
 class ALUOutputData(IntegerData):
     def __init__(self, pspec):