From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Apr 2020 21:02:01 +0000 (+0100)
Subject: dump regfile nicely
X-Git-Tag: div_pipeline~1508
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=639d0038cc2251379be1ed5281cc84dc59e6113d;p=soc.git

dump regfile nicely
---

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index fb227396..b1a90de3 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -85,7 +85,7 @@ class DecoderTestCase(FHDLTestCase):
 
     def run_test_program(self, prog, initial_regs):
         simulator = self.run_tst(prog, initial_regs)
-        print(simulator.gpr)
+        simulator.gpr.dump()
         return simulator
 
 if __name__ == "__main__":