From: Luke Kenneth Casson Leighton Date: Thu, 2 Apr 2020 14:41:41 +0000 (+0100) Subject: -form X-Git-Tag: convert-csv-opcode-to-binary~2989 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63b77f4b59eb355139ca20d6dc6a465e85d75caa;p=libreriscv.git -form --- diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn index a5f9a44af..5f6d686e9 100644 --- a/openpower/isa/fixedarith.mdwn +++ b/openpower/isa/fixedarith.mdwn @@ -238,7 +238,7 @@ Special Registers Altered: # Add to Zero Extended -XO-form +XO-Form * addze RT,RA (OE=0 Rc=0) * addze. RT,RA (OE=0 Rc=1) @@ -255,7 +255,7 @@ Special Registers Altered: # Negate -XO-form +XO-Form * neg RT,RA (OE=0 Rc=0) * neg. RT,RA (OE=0 Rc=1) @@ -271,7 +271,7 @@ Special Registers Altered: # Multiply Low Immediate -D-form +D-Form * mulli RT,RA,SI @@ -284,7 +284,7 @@ Special Registers Altered: # Multiply High Word -XO-form +XO-Form * mulhw RT,RA,RB (Rc=0) * mulhw. RT,RA,RB (Rc=1) @@ -299,7 +299,7 @@ Special Registers Altered: # Multiply Low Word -XO-form +XO-Form * mullw RT,RA,RB (OE=0 Rc=0) * mullw. RT,RA,RB (OE=0 Rc=1) @@ -315,7 +315,7 @@ Special Registers Altered: # Multiply High Word Unsigned -XO-form +XO-Form * mulhwu RT,RA,RB (Rc=0) * mulhwu. RT,RA,RB (Rc=1) @@ -330,7 +330,7 @@ Special Registers Altered: # Divide Word -XO-form +XO-Form * divw RT,RA,RB (OE=0 Rc=0) * divw. RT,RA,RB (OE=0 Rc=1) @@ -349,7 +349,7 @@ Special Registers Altered: # Divide Word Unsigned -XO-form +XO-Form * divwu RT,RA,RB (OE=0 Rc=0) * divwu. RT,RA,RB (OE=0 Rc=1) @@ -368,7 +368,7 @@ Special Registers Altered: # Divide Word Extended -XO-form +XO-Form * divwe RT,RA,RB (OE=0 Rc=0) * divwe. RT,RA,RB (OE=0 Rc=1) @@ -387,7 +387,7 @@ Special Registers Altered: # Divide Word Extended Unsigned -XO-form +XO-Form * divweu RT,RA,RB (OE=0 Rc=0) * divweu. RT,RA,RB (OE=0 Rc=1) @@ -406,7 +406,7 @@ Special Registers Altered: # Modulo Signed Word -X-form +X-Form * modsw RT,RA,RB @@ -421,7 +421,7 @@ Special Registers Altered: # Modulo Unsigned Word -X-form +X-Form * moduw RT,RA,RB @@ -436,7 +436,7 @@ Special Registers Altered: # Deliver A Random Number -X-form +X-Form * darn RT,L @@ -448,7 +448,7 @@ Special Registers Altered: # Multiply Low Doubleword -XO-form +XO-Form * mulld RT,RA,RB (OE=0 Rc=0) * mulld. RT,RA,RB (OE=0 Rc=1) @@ -465,7 +465,7 @@ Special Registers Altered: # Multiply High Doubleword -XO-form +XO-Form * mulhd RT,RA,RB (Rc=0) * mulhd. RT,RA,RB (Rc=1) @@ -479,7 +479,7 @@ Special Registers Altered: # Multiply High Doubleword Unsigned -XO-form +XO-Form * mulhdu RT,RA,RB (Rc=0) * mulhdu. RT,RA,RB (Rc=1) @@ -491,9 +491,9 @@ Special Registers Altered: CR0 (if Rc=1) -# Multiply-Add High Doubleword VA-form +# Multiply-Add High Doubleword VA-Form -VA-form +VA-Form * maddhd RT,RA.RB,RC @@ -507,7 +507,7 @@ Special Registers Altered: # Multiply-Add High Doubleword Unsigned -VA-form +VA-Form * maddhdu RT,RA.RB,RC @@ -521,7 +521,7 @@ Special Registers Altered: # Multiply-Add Low Doubleword -VA-form +VA-Form * maddld RT,RA.RB,RC @@ -536,7 +536,7 @@ Special Registers Altered: # Divide Doubleword -XO-form +XO-Form * divd RT,RA,RB (OE=0 Rc=0) * divd. RT,RA,RB (OE=0 Rc=1) @@ -554,7 +554,7 @@ Special Registers Altered: # Divide Doubleword Unsigned -XO-form +XO-Form * divdu RT,RA,RB (OE=0 Rc=0) * divdu. RT,RA,RB (OE=0 Rc=1) @@ -572,7 +572,7 @@ Special Registers Altered: # Divide Doubleword Extended -XO-form +XO-Form * divde RT,RA,RB (OE=0 Rc=0) * divde. RT,RA,RB (OE=0 Rc=1) @@ -590,7 +590,7 @@ Special Registers Altered: # Divide Doubleword Extended Unsigned -XO-form +XO-Form * divdeu RT,RA,RB (OE=0 Rc=0) * divdeu. RT,RA,RB (OE=0 Rc=1) @@ -608,7 +608,7 @@ Special Registers Altered: # Modulo Signed Doubleword -X-form +X-Form * modsd RT,RA,RB @@ -622,7 +622,7 @@ Special Registers Altered: # Modulo Unsigned Doubleword -X-form +X-Form * modud RT,RA,RB