From: Florent Kermarrec Date: Sat, 2 May 2015 10:55:51 +0000 (+0200) Subject: liteeth: move mac to core X-Git-Tag: 24jan2021_ls180~2271 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63b879797841ae6a7d9accd8f40bdc3681900b62;p=litex.git liteeth: move mac to core --- diff --git a/misoclib/com/liteeth/core/__init__.py b/misoclib/com/liteeth/core/__init__.py index f789ac7e..d099485f 100644 --- a/misoclib/com/liteeth/core/__init__.py +++ b/misoclib/com/liteeth/core/__init__.py @@ -1,5 +1,5 @@ from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.mac import LiteEthMAC +from misoclib.com.liteeth.core.mac import LiteEthMAC from misoclib.com.liteeth.core.arp import LiteEthARP from misoclib.com.liteeth.core.ip import LiteEthIP from misoclib.com.liteeth.core.udp import LiteEthUDP diff --git a/misoclib/com/liteeth/core/mac/__init__.py b/misoclib/com/liteeth/core/mac/__init__.py new file mode 100644 index 00000000..14bbf74b --- /dev/null +++ b/misoclib/com/liteeth/core/mac/__init__.py @@ -0,0 +1,33 @@ +from misoclib.com.liteeth.common import * +from misoclib.com.liteeth.core.mac.common import * +from misoclib.com.liteeth.core.mac.core import LiteEthMACCore +from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface + + +class LiteEthMAC(Module, AutoCSR): + def __init__(self, phy, dw, interface="crossbar", endianness="big", + with_preamble_crc=True): + self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc) + self.csrs = [] + if interface == "crossbar": + self.submodules.crossbar = LiteEthMACCrossbar() + self.submodules.packetizer = LiteEthMACPacketizer() + self.submodules.depacketizer = LiteEthMACDepacketizer() + self.comb += [ + Record.connect(self.crossbar.master.source, self.packetizer.sink), + Record.connect(self.packetizer.source, self.core.sink), + Record.connect(self.core.source, self.depacketizer.sink), + Record.connect(self.depacketizer.source, self.crossbar.master.sink) + ] + elif interface == "wishbone": + self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2) + self.comb += Port.connect(self.interface, self.core) + self.ev, self.bus = self.interface.sram.ev, self.interface.bus + self.csrs = self.interface.get_csrs() + self.core.get_csrs() + elif interface == "dma": + raise NotImplementedError + else: + raise ValueError(interface + " not supported by LiteEthMac!") + + def get_csrs(self): + return self.csrs diff --git a/misoclib/com/liteeth/core/mac/common.py b/misoclib/com/liteeth/core/mac/common.py new file mode 100644 index 00000000..f12cc3e7 --- /dev/null +++ b/misoclib/com/liteeth/core/mac/common.py @@ -0,0 +1,47 @@ +from misoclib.com.liteeth.common import * +from misoclib.com.liteeth.crossbar import LiteEthCrossbar + + +class LiteEthMACDepacketizer(Depacketizer): + def __init__(self): + Depacketizer.__init__(self, + eth_phy_description(8), + eth_mac_description(8), + mac_header) + + +class LiteEthMACPacketizer(Packetizer): + def __init__(self): + Packetizer.__init__(self, + eth_mac_description(8), + eth_phy_description(8), + mac_header) + + +class LiteEthMACMasterPort: + def __init__(self, dw): + self.source = Source(eth_mac_description(dw)) + self.sink = Sink(eth_mac_description(dw)) + + +class LiteEthMACSlavePort: + def __init__(self, dw): + self.sink = Sink(eth_mac_description(dw)) + self.source = Source(eth_mac_description(dw)) + + +class LiteEthMACUserPort(LiteEthMACSlavePort): + def __init__(self, dw): + LiteEthMACSlavePort.__init__(self, dw) + + +class LiteEthMACCrossbar(LiteEthCrossbar): + def __init__(self): + LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type") + + def get_port(self, ethernet_type): + port = LiteEthMACUserPort(8) + if ethernet_type in self.users.keys(): + raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type)) + self.users[ethernet_type] = port + return port diff --git a/misoclib/com/liteeth/core/mac/core/__init__.py b/misoclib/com/liteeth/core/mac/core/__init__.py new file mode 100644 index 00000000..f31cafa2 --- /dev/null +++ b/misoclib/com/liteeth/core/mac/core/__init__.py @@ -0,0 +1,95 @@ +from misoclib.com.liteeth.common import * +from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be +from misoclib.com.liteeth.phy.sim import LiteEthPHYSim + + +class LiteEthMACCore(Module, AutoCSR): + def __init__(self, phy, dw, endianness="big", + with_preamble_crc=True, + with_padding=True): + if dw < phy.dw: + raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw)) + + rx_pipeline = [phy] + tx_pipeline = [phy] + + # Interpacket gap + tx_gap_inserter = gap.LiteEthMACGap(phy.dw) + rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True) + self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx") + self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx") + + tx_pipeline += [tx_gap_inserter] + rx_pipeline += [rx_gap_checker] + + # Preamble / CRC + if isinstance(phy, LiteEthPHYSim): + # In simulation, avoid CRC/Preamble to enable direct connection + # to the Ethernet tap. + self._preamble_crc = CSRStatus(reset=1) + elif with_preamble_crc: + self._preamble_crc = CSRStatus(reset=1) + # Preamble insert/check + preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw) + preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw) + self.submodules += RenameClockDomains(preamble_inserter, "eth_tx") + self.submodules += RenameClockDomains(preamble_checker, "eth_rx") + + # CRC insert/check + crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw)) + crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw)) + self.submodules += RenameClockDomains(crc32_inserter, "eth_tx") + self.submodules += RenameClockDomains(crc32_checker, "eth_rx") + + tx_pipeline += [preamble_inserter, crc32_inserter] + rx_pipeline += [preamble_checker, crc32_checker] + + # Padding + if with_padding: + padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60) + padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60) + self.submodules += RenameClockDomains(padding_inserter, "eth_tx") + self.submodules += RenameClockDomains(padding_checker, "eth_rx") + + tx_pipeline += [padding_inserter] + rx_pipeline += [padding_checker] + + # Delimiters + if dw != 8: + tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw) + rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw) + self.submodules += RenameClockDomains(tx_last_be, "eth_tx") + self.submodules += RenameClockDomains(rx_last_be, "eth_rx") + + tx_pipeline += [tx_last_be] + rx_pipeline += [rx_last_be] + + # Converters + if dw != phy.dw: + reverse = endianness == "big" + tx_converter = Converter(eth_phy_description(dw), + eth_phy_description(phy.dw), + reverse=reverse) + rx_converter = Converter(eth_phy_description(phy.dw), + eth_phy_description(dw), + reverse=reverse) + self.submodules += RenameClockDomains(tx_converter, "eth_tx") + self.submodules += RenameClockDomains(rx_converter, "eth_rx") + + tx_pipeline += [tx_converter] + rx_pipeline += [rx_converter] + + # Cross Domain Crossing + tx_cdc = AsyncFIFO(eth_phy_description(dw), 64) + rx_cdc = AsyncFIFO(eth_phy_description(dw), 64) + self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) + self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"}) + + tx_pipeline += [tx_cdc] + rx_pipeline += [rx_cdc] + + # Graph + self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline)) + self.submodules.rx_pipeline = Pipeline(*rx_pipeline) + + self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source diff --git a/misoclib/com/liteeth/core/mac/core/crc.py b/misoclib/com/liteeth/core/mac/core/crc.py new file mode 100644 index 00000000..ba7c5319 --- /dev/null +++ b/misoclib/com/liteeth/core/mac/core/crc.py @@ -0,0 +1,282 @@ +from misoclib.com.liteeth.common import * + + +class LiteEthMACCRCEngine(Module): + """Cyclic Redundancy Check Engine + + Compute next CRC value from last CRC value and data input using + an optimized asynchronous LFSR. + + Parameters + ---------- + data_width : int + Width of the data bus. + width : int + Width of the CRC. + polynom : int + Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC) + + Attributes + ---------- + data : in + Data input. + last : in + last CRC value. + next : + next CRC value. + """ + def __init__(self, data_width, width, polynom): + self.data = Signal(data_width) + self.last = Signal(width) + self.next = Signal(width) + + # # # + + def _optimize_eq(l): + """ + Replace even numbers of XORs in the equation + with an equivalent XOR + """ + d = OrderedDict() + for e in l: + if e in d: + d[e] += 1 + else: + d[e] = 1 + r = [] + for key, value in d.items(): + if value%2 != 0: + r.append(key) + return r + + # compute and optimize CRC's LFSR + curval = [[("state", i)] for i in range(width)] + for i in range(data_width): + feedback = curval.pop() + [("din", i)] + for j in range(width-1): + if (polynom & (1<<(j+1))): + curval[j] += feedback + curval[j] = _optimize_eq(curval[j]) + curval.insert(0, feedback) + + # implement logic + for i in range(width): + xors = [] + for t, n in curval[i]: + if t == "state": + xors += [self.last[n]] + elif t == "din": + xors += [self.data[n]] + self.comb += self.next[i].eq(optree("^", xors)) + + +@DecorateModule(InsertReset) +@DecorateModule(InsertCE) +class LiteEthMACCRC32(Module): + """IEEE 802.3 CRC + + Implement an IEEE 802.3 CRC generator/checker. + + Parameters + ---------- + data_width : int + Width of the data bus. + + Attributes + ---------- + d : in + Data input. + value : out + CRC value (used for generator). + error : out + CRC error (used for checker). + """ + width = 32 + polynom = 0x04C11DB7 + init = 2**width-1 + check = 0xC704DD7B + def __init__(self, data_width): + self.data = Signal(data_width) + self.value = Signal(self.width) + self.error = Signal() + + # # # + + self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom) + reg = Signal(self.width, reset=self.init) + self.sync += reg.eq(self.engine.next) + self.comb += [ + self.engine.data.eq(self.data), + self.engine.last.eq(reg), + + self.value.eq(~reg[::-1]), + self.error.eq(self.engine.next != self.check) + ] + + +class LiteEthMACCRCInserter(Module): + """CRC Inserter + + Append a CRC at the end of each packet. + + Parameters + ---------- + description : description + description of the dataflow. + + Attributes + ---------- + sink : in + Packets input without CRC. + source : out + Packets output with CRC. + """ + def __init__(self, crc_class, description): + self.sink = sink = Sink(description) + self.source = source = Source(description) + self.busy = Signal() + + # # # + + dw = flen(sink.data) + crc = crc_class(dw) + fsm = FSM(reset_state="IDLE") + self.submodules += crc, fsm + + fsm.act("IDLE", + crc.reset.eq(1), + sink.ack.eq(1), + If(sink.stb & sink.sop, + sink.ack.eq(0), + NextState("COPY"), + ) + ) + fsm.act("COPY", + crc.ce.eq(sink.stb & source.ack), + crc.data.eq(sink.data), + Record.connect(sink, source), + source.eop.eq(0), + If(sink.stb & sink.eop & source.ack, + NextState("INSERT"), + ) + ) + ratio = crc.width//dw + if ratio > 1: + cnt = Signal(max=ratio, reset=ratio-1) + cnt_done = Signal() + fsm.act("INSERT", + source.stb.eq(1), + chooser(crc.value, cnt, source.data, reverse=True), + If(cnt_done, + source.eop.eq(1), + If(source.ack, NextState("IDLE")) + ) + ) + self.comb += cnt_done.eq(cnt == 0) + self.sync += \ + If(fsm.ongoing("IDLE"), + cnt.eq(cnt.reset) + ).Elif(fsm.ongoing("INSERT") & ~cnt_done, + cnt.eq(cnt - source.ack) + ) + else: + fsm.act("INSERT", + source.stb.eq(1), + source.eop.eq(1), + source.data.eq(crc.value), + If(source.ack, NextState("IDLE")) + ) + self.comb += self.busy.eq(~fsm.ongoing("IDLE")) + + +class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter): + def __init__(self, description): + LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, description) + + +class LiteEthMACCRCChecker(Module): + """CRC Checker + + Check CRC at the end of each packet. + + Parameters + ---------- + description : description + description of the dataflow. + + Attributes + ---------- + sink : in + Packets input with CRC. + source : out + Packets output without CRC and "error" set to 0 + on eop when CRC OK / set to 1 when CRC KO. + """ + def __init__(self, crc_class, description): + self.sink = sink = Sink(description) + self.source = source = Source(description) + self.busy = Signal() + + # # # + + dw = flen(sink.data) + crc = crc_class(dw) + self.submodules += crc + ratio = crc.width//dw + + error = Signal() + fifo = InsertReset(SyncFIFO(description, ratio + 1)) + self.submodules += fifo + + fsm = FSM(reset_state="RESET") + self.submodules += fsm + + fifo_in = Signal() + fifo_out = Signal() + fifo_full = Signal() + + self.comb += [ + fifo_full.eq(fifo.fifo.level == ratio), + fifo_in.eq(sink.stb & (~fifo_full | fifo_out)), + fifo_out.eq(source.stb & source.ack), + + Record.connect(sink, fifo.sink), + fifo.sink.stb.eq(fifo_in), + self.sink.ack.eq(fifo_in), + + source.stb.eq(sink.stb & fifo_full), + source.sop.eq(fifo.source.sop), + source.eop.eq(sink.eop), + fifo.source.ack.eq(fifo_out), + source.payload.eq(fifo.source.payload), + + source.error.eq(sink.error | crc.error), + ] + + fsm.act("RESET", + crc.reset.eq(1), + fifo.reset.eq(1), + NextState("IDLE"), + ) + fsm.act("IDLE", + crc.data.eq(sink.data), + If(sink.stb & sink.sop & sink.ack, + crc.ce.eq(1), + NextState("COPY") + ) + ) + fsm.act("COPY", + crc.data.eq(sink.data), + If(sink.stb & sink.ack, + crc.ce.eq(1), + If(sink.eop, + NextState("RESET") + ) + ) + ) + self.comb += self.busy.eq(~fsm.ongoing("IDLE")) + + +class LiteEthMACCRC32Checker(LiteEthMACCRCChecker): + def __init__(self, description): + LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, description) diff --git a/misoclib/com/liteeth/core/mac/core/gap.py b/misoclib/com/liteeth/core/mac/core/gap.py new file mode 100644 index 00000000..c1bd9162 --- /dev/null +++ b/misoclib/com/liteeth/core/mac/core/gap.py @@ -0,0 +1,27 @@ +from misoclib.com.liteeth.common import * + +class LiteEthMACGap(Module): + def __init__(self, dw, ack_on_gap=False): + self.sink = sink = Sink(eth_phy_description(dw)) + self.source = source = Source(eth_phy_description(dw)) + + # # # + + gap = math.ceil(eth_interpacket_gap/(dw//8)) + self.submodules.counter = counter = Counter(max=gap) + + self.submodules.fsm = fsm = FSM(reset_state="COPY") + fsm.act("COPY", + counter.reset.eq(1), + Record.connect(sink, source), + If(sink.stb & sink.eop & sink.ack, + NextState("GAP") + ) + ) + fsm.act("GAP", + counter.ce.eq(1), + sink.ack.eq(int(ack_on_gap)), + If(counter.value == (gap-1), + NextState("COPY") + ) + ) diff --git a/misoclib/com/liteeth/core/mac/core/last_be.py b/misoclib/com/liteeth/core/mac/core/last_be.py new file mode 100644 index 00000000..42f7c641 --- /dev/null +++ b/misoclib/com/liteeth/core/mac/core/last_be.py @@ -0,0 +1,43 @@ +from misoclib.com.liteeth.common import * + + +class LiteEthMACTXLastBE(Module): + def __init__(self, dw): + self.sink = sink = Sink(eth_phy_description(dw)) + self.source = source = Source(eth_phy_description(dw)) + + # # # + + ongoing = Signal() + self.sync += \ + If(sink.stb & sink.ack, + If(sink.sop, + ongoing.eq(1) + ).Elif(sink.last_be, + ongoing.eq(0) + ) + ) + self.comb += [ + source.stb.eq(sink.stb & (sink.sop | ongoing)), + source.sop.eq(sink.sop), + source.eop.eq(sink.last_be), + source.data.eq(sink.data), + sink.ack.eq(source.ack) + ] + + +class LiteEthMACRXLastBE(Module): + def __init__(self, dw): + self.sink = sink = Sink(eth_phy_description(dw)) + self.source = source = Source(eth_phy_description(dw)) + + # # # + + self.comb += [ + source.stb.eq(sink.stb), + source.sop.eq(sink.sop), + source.eop.eq(sink.eop), + source.data.eq(sink.data), + source.last_be.eq(sink.eop), + sink.ack.eq(source.ack) + ] diff --git a/misoclib/com/liteeth/core/mac/core/padding.py b/misoclib/com/liteeth/core/mac/core/padding.py new file mode 100644 index 00000000..38b2a3da --- /dev/null +++ b/misoclib/com/liteeth/core/mac/core/padding.py @@ -0,0 +1,56 @@ +from misoclib.com.liteeth.common import * + + +class LiteEthMACPaddingInserter(Module): + def __init__(self, dw, padding): + self.sink = sink = Sink(eth_phy_description(dw)) + self.source = source = Source(eth_phy_description(dw)) + + # # # + + padding_limit = math.ceil(padding/(dw/8))-1 + + self.submodules.counter = counter = Counter(16, reset=1) + counter_done = Signal() + self.comb += [ + counter.reset.eq(sink.stb & sink.sop & sink.ack), + counter.ce.eq(source.stb & source.ack), + counter_done.eq(counter.value >= padding_limit), + ] + + self.submodules.fsm = fsm = FSM(reset_state="IDLE") + fsm.act("IDLE", + Record.connect(sink, source), + If(source.stb & source.ack, + counter.ce.eq(1), + If(sink.eop, + If(~counter_done, + source.eop.eq(0), + NextState("PADDING") + ) + ) + ) + ) + fsm.act("PADDING", + source.stb.eq(1), + source.eop.eq(counter_done), + source.data.eq(0), + If(source.ack, + If(counter_done, + NextState("IDLE") + ) + ) + ) + + +class LiteEthMACPaddingChecker(Module): + def __init__(self, dw, packet_min_length): + self.sink = sink = Sink(eth_phy_description(dw)) + self.source = source = Source(eth_phy_description(dw)) + + # # # + + # XXX see if we should drop the packet when + # payload size < minimum ethernet payload size + self.comb += Record.connect(sink, source) + diff --git a/misoclib/com/liteeth/core/mac/core/preamble.py b/misoclib/com/liteeth/core/mac/core/preamble.py new file mode 100644 index 00000000..18e86f83 --- /dev/null +++ b/misoclib/com/liteeth/core/mac/core/preamble.py @@ -0,0 +1,141 @@ +from misoclib.com.liteeth.common import * + + +class LiteEthMACPreambleInserter(Module): + def __init__(self, dw): + self.sink = Sink(eth_phy_description(dw)) + self.source = Source(eth_phy_description(dw)) + + # # # + + preamble = Signal(64, reset=eth_preamble) + cnt_max = (64//dw)-1 + cnt = Signal(max=cnt_max+1) + clr_cnt = Signal() + inc_cnt = Signal() + + self.sync += \ + If(clr_cnt, + cnt.eq(0) + ).Elif(inc_cnt, + cnt.eq(cnt+1) + ) + + fsm = FSM(reset_state="IDLE") + self.submodules += fsm + fsm.act("IDLE", + self.sink.ack.eq(1), + clr_cnt.eq(1), + If(self.sink.stb & self.sink.sop, + self.sink.ack.eq(0), + NextState("INSERT"), + ) + ) + fsm.act("INSERT", + self.source.stb.eq(1), + self.source.sop.eq(cnt == 0), + chooser(preamble, cnt, self.source.data), + If(cnt == cnt_max, + If(self.source.ack, NextState("COPY")) + ).Else( + inc_cnt.eq(self.source.ack) + ) + ) + fsm.act("COPY", + Record.connect(self.sink, self.source), + self.source.sop.eq(0), + + If(self.sink.stb & self.sink.eop & self.source.ack, + NextState("IDLE"), + ) + ) + + +class LiteEthMACPreambleChecker(Module): + def __init__(self, dw): + self.sink = Sink(eth_phy_description(dw)) + self.source = Source(eth_phy_description(dw)) + + # # # + + preamble = Signal(64, reset=eth_preamble) + cnt_max = (64//dw) - 1 + cnt = Signal(max=cnt_max+1) + clr_cnt = Signal() + inc_cnt = Signal() + + self.sync += \ + If(clr_cnt, + cnt.eq(0) + ).Elif(inc_cnt, + cnt.eq(cnt+1) + ) + + discard = Signal() + clr_discard = Signal() + set_discard = Signal() + + self.sync += \ + If(clr_discard, + discard.eq(0) + ).Elif(set_discard, + discard.eq(1) + ) + + sop = Signal() + clr_sop = Signal() + set_sop = Signal() + self.sync += \ + If(clr_sop, + sop.eq(0) + ).Elif(set_sop, + sop.eq(1) + ) + + ref = Signal(dw) + match = Signal() + self.comb += [ + chooser(preamble, cnt, ref), + match.eq(self.sink.data == ref) + ] + + fsm = FSM(reset_state="IDLE") + self.submodules += fsm + + fsm.act("IDLE", + self.sink.ack.eq(1), + clr_cnt.eq(1), + clr_discard.eq(1), + If(self.sink.stb & self.sink.sop, + clr_cnt.eq(0), + inc_cnt.eq(1), + clr_discard.eq(0), + set_discard.eq(~match), + NextState("CHECK"), + ) + ) + fsm.act("CHECK", + self.sink.ack.eq(1), + If(self.sink.stb, + set_discard.eq(~match), + If(cnt == cnt_max, + If(discard | (~match), + NextState("IDLE") + ).Else( + set_sop.eq(1), + NextState("COPY") + ) + ).Else( + inc_cnt.eq(1) + ) + ) + ) + fsm.act("COPY", + Record.connect(self.sink, self.source), + self.source.sop.eq(sop), + clr_sop.eq(self.source.stb & self.source.ack), + + If(self.source.stb & self.source.eop & self.source.ack, + NextState("IDLE"), + ) + ) diff --git a/misoclib/com/liteeth/core/mac/frontend/__init__.py b/misoclib/com/liteeth/core/mac/frontend/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/misoclib/com/liteeth/core/mac/frontend/sram.py b/misoclib/com/liteeth/core/mac/frontend/sram.py new file mode 100644 index 00000000..fc3d8c27 --- /dev/null +++ b/misoclib/com/liteeth/core/mac/frontend/sram.py @@ -0,0 +1,234 @@ +from misoclib.com.liteeth.common import * + +from migen.bank.description import * +from migen.bank.eventmanager import * + + +class LiteEthMACSRAMWriter(Module, AutoCSR): + def __init__(self, dw, depth, nslots=2): + self.sink = sink = Sink(eth_phy_description(dw)) + self.crc_error = Signal() + + slotbits = max(log2_int(nslots), 1) + lengthbits = log2_int(depth*4) # length in bytes + + self._slot = CSRStatus(slotbits) + self._length = CSRStatus(lengthbits) + + self.submodules.ev = EventManager() + self.ev.available = EventSourceLevel() + self.ev.finalize() + + # # # + + # packet dropped if no slot available + sink.ack.reset = 1 + + # length computation + increment = Signal(3) + self.comb += \ + If(sink.last_be[3], + increment.eq(1) + ).Elif(sink.last_be[2], + increment.eq(2) + ).Elif(sink.last_be[1], + increment.eq(3) + ).Else( + increment.eq(4) + ) + counter = Counter(lengthbits, increment=increment) + self.submodules += counter + + # slot computation + slot = Counter(slotbits) + self.submodules += slot + + ongoing = Signal() + + # status fifo + fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots) + self.submodules += fifo + + # fsm + fsm = FSM(reset_state="IDLE") + self.submodules += fsm + + fsm.act("IDLE", + If(sink.stb & sink.sop, + If(fifo.sink.ack, + ongoing.eq(1), + counter.ce.eq(1), + NextState("WRITE") + ) + ) + ) + fsm.act("WRITE", + counter.ce.eq(sink.stb), + ongoing.eq(1), + If(sink.stb & sink.eop, + If((sink.error & sink.last_be) != 0, + NextState("DISCARD") + ).Else( + NextState("TERMINATE") + ) + ) + ) + fsm.act("DISCARD", + counter.reset.eq(1), + NextState("IDLE") + ) + self.comb += [ + fifo.sink.slot.eq(slot.value), + fifo.sink.length.eq(counter.value) + ] + fsm.act("TERMINATE", + counter.reset.eq(1), + slot.ce.eq(1), + fifo.sink.stb.eq(1), + NextState("IDLE") + ) + self.comb += [ + fifo.source.ack.eq(self.ev.available.clear), + self.ev.available.trigger.eq(fifo.source.stb), + self._slot.status.eq(fifo.source.slot), + self._length.status.eq(fifo.source.length), + ] + + # memory + mems = [None]*nslots + ports = [None]*nslots + for n in range(nslots): + mems[n] = Memory(dw, depth) + ports[n] = mems[n].get_port(write_capable=True) + self.specials += ports[n] + self.mems = mems + + cases = {} + for n, port in enumerate(ports): + cases[n] = [ + ports[n].adr.eq(counter.value[2:]), + ports[n].dat_w.eq(sink.data), + If(sink.stb & ongoing, + ports[n].we.eq(0xf) + ) + ] + self.comb += Case(slot.value, cases) + + +class LiteEthMACSRAMReader(Module, AutoCSR): + def __init__(self, dw, depth, nslots=2): + self.source = source = Source(eth_phy_description(dw)) + + slotbits = max(log2_int(nslots), 1) + lengthbits = log2_int(depth*4) # length in bytes + self.lengthbits = lengthbits + + self._start = CSR() + self._ready = CSRStatus() + self._slot = CSRStorage(slotbits) + self._length = CSRStorage(lengthbits) + + self.submodules.ev = EventManager() + self.ev.done = EventSourcePulse() + self.ev.finalize() + + # # # + + # command fifo + fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots) + self.submodules += fifo + self.comb += [ + fifo.sink.stb.eq(self._start.re), + fifo.sink.slot.eq(self._slot.storage), + fifo.sink.length.eq(self._length.storage), + self._ready.status.eq(fifo.sink.ack) + ] + + # length computation + self.submodules.counter = counter = Counter(lengthbits, increment=4) + + # fsm + first = Signal() + last = Signal() + last_d = Signal() + + fsm = FSM(reset_state="IDLE") + self.submodules += fsm + + fsm.act("IDLE", + counter.reset.eq(1), + If(fifo.source.stb, + NextState("CHECK") + ) + ) + fsm.act("CHECK", + If(~last_d, + NextState("SEND"), + ).Else( + NextState("END"), + ) + ) + length_lsb = fifo.source.length[0:2] + self.comb += [ + If(last, + If(length_lsb == 3, + source.last_be.eq(0b0010) + ).Elif(length_lsb == 2, + source.last_be.eq(0b0100) + ).Elif(length_lsb == 1, + source.last_be.eq(0b1000) + ).Else( + source.last_be.eq(0b0001) + ) + ) + ] + fsm.act("SEND", + source.stb.eq(1), + source.sop.eq(first), + source.eop.eq(last), + If(source.ack, + counter.ce.eq(~last), + NextState("CHECK") + ) + ) + fsm.act("END", + fifo.source.ack.eq(1), + self.ev.done.trigger.eq(1), + NextState("IDLE") + ) + + # first/last computation + self.sync += [ + If(fsm.ongoing("IDLE"), + first.eq(1) + ).Elif(source.stb & source.ack, + first.eq(0) + ) + ] + self.comb += last.eq((counter.value + 4) >= fifo.source.length) + self.sync += last_d.eq(last) + + # memory + rd_slot = fifo.source.slot + + mems = [None]*nslots + ports = [None]*nslots + for n in range(nslots): + mems[n] = Memory(dw, depth) + ports[n] = mems[n].get_port() + self.specials += ports[n] + self.mems = mems + + cases = {} + for n, port in enumerate(ports): + self.comb += ports[n].adr.eq(counter.value[2:]) + cases[n] = [source.data.eq(port.dat_r)] + self.comb += Case(rd_slot, cases) + + +class LiteEthMACSRAM(Module, AutoCSR): + def __init__(self, dw, depth, nrxslots, ntxslots): + self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots) + self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots) + self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev) + self.sink, self.source = self.writer.sink, self.reader.source diff --git a/misoclib/com/liteeth/core/mac/frontend/wishbone.py b/misoclib/com/liteeth/core/mac/frontend/wishbone.py new file mode 100644 index 00000000..48a8f1d2 --- /dev/null +++ b/misoclib/com/liteeth/core/mac/frontend/wishbone.py @@ -0,0 +1,41 @@ +from misoclib.com.liteeth.common import * +from misoclib.com.liteeth.core.mac.frontend import sram + +from migen.bus import wishbone +from migen.fhdl.simplify import FullMemoryWE + + +class LiteEthMACWishboneInterface(Module, AutoCSR): + def __init__(self, dw, nrxslots=2, ntxslots=2): + self.sink = Sink(eth_phy_description(dw)) + self.source = Source(eth_phy_description(dw)) + self.bus = wishbone.Interface() + + # # # + + # storage in SRAM + sram_depth = buffer_depth//(dw//8) + self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots) + self.comb += [ + Record.connect(self.sink, self.sram.sink), + Record.connect(self.sram.source, self.source) + ] + + # Wishbone interface + wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True) + for n in range(nrxslots)] + # TODO: FullMemoryWE should move to Mibuild + wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False)) + for n in range(ntxslots)] + wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs + + wb_slaves = [] + decoderoffset = log2_int(sram_depth) + decoderbits = log2_int(len(wb_sram_ifs)) + for n, wb_sram_if in enumerate(wb_sram_ifs): + def slave_filter(a, v=n): + return a[decoderoffset:decoderoffset+decoderbits] == v + wb_slaves.append((slave_filter, wb_sram_if.bus)) + self.submodules += wb_sram_if + wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True) + self.submodules += wb_con diff --git a/misoclib/com/liteeth/mac/__init__.py b/misoclib/com/liteeth/mac/__init__.py deleted file mode 100644 index 5c2a0675..00000000 --- a/misoclib/com/liteeth/mac/__init__.py +++ /dev/null @@ -1,33 +0,0 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.mac.common import * -from misoclib.com.liteeth.mac.core import LiteEthMACCore -from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface - - -class LiteEthMAC(Module, AutoCSR): - def __init__(self, phy, dw, interface="crossbar", endianness="big", - with_preamble_crc=True): - self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc) - self.csrs = [] - if interface == "crossbar": - self.submodules.crossbar = LiteEthMACCrossbar() - self.submodules.packetizer = LiteEthMACPacketizer() - self.submodules.depacketizer = LiteEthMACDepacketizer() - self.comb += [ - Record.connect(self.crossbar.master.source, self.packetizer.sink), - Record.connect(self.packetizer.source, self.core.sink), - Record.connect(self.core.source, self.depacketizer.sink), - Record.connect(self.depacketizer.source, self.crossbar.master.sink) - ] - elif interface == "wishbone": - self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2) - self.comb += Port.connect(self.interface, self.core) - self.ev, self.bus = self.interface.sram.ev, self.interface.bus - self.csrs = self.interface.get_csrs() + self.core.get_csrs() - elif interface == "dma": - raise NotImplementedError - else: - raise ValueError(interface + " not supported by LiteEthMac!") - - def get_csrs(self): - return self.csrs diff --git a/misoclib/com/liteeth/mac/common.py b/misoclib/com/liteeth/mac/common.py deleted file mode 100644 index f12cc3e7..00000000 --- a/misoclib/com/liteeth/mac/common.py +++ /dev/null @@ -1,47 +0,0 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.crossbar import LiteEthCrossbar - - -class LiteEthMACDepacketizer(Depacketizer): - def __init__(self): - Depacketizer.__init__(self, - eth_phy_description(8), - eth_mac_description(8), - mac_header) - - -class LiteEthMACPacketizer(Packetizer): - def __init__(self): - Packetizer.__init__(self, - eth_mac_description(8), - eth_phy_description(8), - mac_header) - - -class LiteEthMACMasterPort: - def __init__(self, dw): - self.source = Source(eth_mac_description(dw)) - self.sink = Sink(eth_mac_description(dw)) - - -class LiteEthMACSlavePort: - def __init__(self, dw): - self.sink = Sink(eth_mac_description(dw)) - self.source = Source(eth_mac_description(dw)) - - -class LiteEthMACUserPort(LiteEthMACSlavePort): - def __init__(self, dw): - LiteEthMACSlavePort.__init__(self, dw) - - -class LiteEthMACCrossbar(LiteEthCrossbar): - def __init__(self): - LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type") - - def get_port(self, ethernet_type): - port = LiteEthMACUserPort(8) - if ethernet_type in self.users.keys(): - raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type)) - self.users[ethernet_type] = port - return port diff --git a/misoclib/com/liteeth/mac/core/__init__.py b/misoclib/com/liteeth/mac/core/__init__.py deleted file mode 100644 index f8b18f73..00000000 --- a/misoclib/com/liteeth/mac/core/__init__.py +++ /dev/null @@ -1,95 +0,0 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be -from misoclib.com.liteeth.phy.sim import LiteEthPHYSim - - -class LiteEthMACCore(Module, AutoCSR): - def __init__(self, phy, dw, endianness="big", - with_preamble_crc=True, - with_padding=True): - if dw < phy.dw: - raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw)) - - rx_pipeline = [phy] - tx_pipeline = [phy] - - # Interpacket gap - tx_gap_inserter = gap.LiteEthMACGap(phy.dw) - rx_gap_checker = gap.LiteEthMACGap(phy.dw, ack_on_gap=True) - self.submodules += RenameClockDomains(tx_gap_inserter, "eth_tx") - self.submodules += RenameClockDomains(rx_gap_checker, "eth_rx") - - tx_pipeline += [tx_gap_inserter] - rx_pipeline += [rx_gap_checker] - - # Preamble / CRC - if isinstance(phy, LiteEthPHYSim): - # In simulation, avoid CRC/Preamble to enable direct connection - # to the Ethernet tap. - self._preamble_crc = CSRStatus(reset=1) - elif with_preamble_crc: - self._preamble_crc = CSRStatus(reset=1) - # Preamble insert/check - preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw) - preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw) - self.submodules += RenameClockDomains(preamble_inserter, "eth_tx") - self.submodules += RenameClockDomains(preamble_checker, "eth_rx") - - # CRC insert/check - crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(phy.dw)) - crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(phy.dw)) - self.submodules += RenameClockDomains(crc32_inserter, "eth_tx") - self.submodules += RenameClockDomains(crc32_checker, "eth_rx") - - tx_pipeline += [preamble_inserter, crc32_inserter] - rx_pipeline += [preamble_checker, crc32_checker] - - # Padding - if with_padding: - padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60) - padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60) - self.submodules += RenameClockDomains(padding_inserter, "eth_tx") - self.submodules += RenameClockDomains(padding_checker, "eth_rx") - - tx_pipeline += [padding_inserter] - rx_pipeline += [padding_checker] - - # Delimiters - if dw != 8: - tx_last_be = last_be.LiteEthMACTXLastBE(phy.dw) - rx_last_be = last_be.LiteEthMACRXLastBE(phy.dw) - self.submodules += RenameClockDomains(tx_last_be, "eth_tx") - self.submodules += RenameClockDomains(rx_last_be, "eth_rx") - - tx_pipeline += [tx_last_be] - rx_pipeline += [rx_last_be] - - # Converters - if dw != phy.dw: - reverse = endianness == "big" - tx_converter = Converter(eth_phy_description(dw), - eth_phy_description(phy.dw), - reverse=reverse) - rx_converter = Converter(eth_phy_description(phy.dw), - eth_phy_description(dw), - reverse=reverse) - self.submodules += RenameClockDomains(tx_converter, "eth_tx") - self.submodules += RenameClockDomains(rx_converter, "eth_rx") - - tx_pipeline += [tx_converter] - rx_pipeline += [rx_converter] - - # Cross Domain Crossing - tx_cdc = AsyncFIFO(eth_phy_description(dw), 64) - rx_cdc = AsyncFIFO(eth_phy_description(dw), 64) - self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) - self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"}) - - tx_pipeline += [tx_cdc] - rx_pipeline += [rx_cdc] - - # Graph - self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline)) - self.submodules.rx_pipeline = Pipeline(*rx_pipeline) - - self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source diff --git a/misoclib/com/liteeth/mac/core/crc.py b/misoclib/com/liteeth/mac/core/crc.py deleted file mode 100644 index ba7c5319..00000000 --- a/misoclib/com/liteeth/mac/core/crc.py +++ /dev/null @@ -1,282 +0,0 @@ -from misoclib.com.liteeth.common import * - - -class LiteEthMACCRCEngine(Module): - """Cyclic Redundancy Check Engine - - Compute next CRC value from last CRC value and data input using - an optimized asynchronous LFSR. - - Parameters - ---------- - data_width : int - Width of the data bus. - width : int - Width of the CRC. - polynom : int - Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC) - - Attributes - ---------- - data : in - Data input. - last : in - last CRC value. - next : - next CRC value. - """ - def __init__(self, data_width, width, polynom): - self.data = Signal(data_width) - self.last = Signal(width) - self.next = Signal(width) - - # # # - - def _optimize_eq(l): - """ - Replace even numbers of XORs in the equation - with an equivalent XOR - """ - d = OrderedDict() - for e in l: - if e in d: - d[e] += 1 - else: - d[e] = 1 - r = [] - for key, value in d.items(): - if value%2 != 0: - r.append(key) - return r - - # compute and optimize CRC's LFSR - curval = [[("state", i)] for i in range(width)] - for i in range(data_width): - feedback = curval.pop() + [("din", i)] - for j in range(width-1): - if (polynom & (1<<(j+1))): - curval[j] += feedback - curval[j] = _optimize_eq(curval[j]) - curval.insert(0, feedback) - - # implement logic - for i in range(width): - xors = [] - for t, n in curval[i]: - if t == "state": - xors += [self.last[n]] - elif t == "din": - xors += [self.data[n]] - self.comb += self.next[i].eq(optree("^", xors)) - - -@DecorateModule(InsertReset) -@DecorateModule(InsertCE) -class LiteEthMACCRC32(Module): - """IEEE 802.3 CRC - - Implement an IEEE 802.3 CRC generator/checker. - - Parameters - ---------- - data_width : int - Width of the data bus. - - Attributes - ---------- - d : in - Data input. - value : out - CRC value (used for generator). - error : out - CRC error (used for checker). - """ - width = 32 - polynom = 0x04C11DB7 - init = 2**width-1 - check = 0xC704DD7B - def __init__(self, data_width): - self.data = Signal(data_width) - self.value = Signal(self.width) - self.error = Signal() - - # # # - - self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom) - reg = Signal(self.width, reset=self.init) - self.sync += reg.eq(self.engine.next) - self.comb += [ - self.engine.data.eq(self.data), - self.engine.last.eq(reg), - - self.value.eq(~reg[::-1]), - self.error.eq(self.engine.next != self.check) - ] - - -class LiteEthMACCRCInserter(Module): - """CRC Inserter - - Append a CRC at the end of each packet. - - Parameters - ---------- - description : description - description of the dataflow. - - Attributes - ---------- - sink : in - Packets input without CRC. - source : out - Packets output with CRC. - """ - def __init__(self, crc_class, description): - self.sink = sink = Sink(description) - self.source = source = Source(description) - self.busy = Signal() - - # # # - - dw = flen(sink.data) - crc = crc_class(dw) - fsm = FSM(reset_state="IDLE") - self.submodules += crc, fsm - - fsm.act("IDLE", - crc.reset.eq(1), - sink.ack.eq(1), - If(sink.stb & sink.sop, - sink.ack.eq(0), - NextState("COPY"), - ) - ) - fsm.act("COPY", - crc.ce.eq(sink.stb & source.ack), - crc.data.eq(sink.data), - Record.connect(sink, source), - source.eop.eq(0), - If(sink.stb & sink.eop & source.ack, - NextState("INSERT"), - ) - ) - ratio = crc.width//dw - if ratio > 1: - cnt = Signal(max=ratio, reset=ratio-1) - cnt_done = Signal() - fsm.act("INSERT", - source.stb.eq(1), - chooser(crc.value, cnt, source.data, reverse=True), - If(cnt_done, - source.eop.eq(1), - If(source.ack, NextState("IDLE")) - ) - ) - self.comb += cnt_done.eq(cnt == 0) - self.sync += \ - If(fsm.ongoing("IDLE"), - cnt.eq(cnt.reset) - ).Elif(fsm.ongoing("INSERT") & ~cnt_done, - cnt.eq(cnt - source.ack) - ) - else: - fsm.act("INSERT", - source.stb.eq(1), - source.eop.eq(1), - source.data.eq(crc.value), - If(source.ack, NextState("IDLE")) - ) - self.comb += self.busy.eq(~fsm.ongoing("IDLE")) - - -class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter): - def __init__(self, description): - LiteEthMACCRCInserter.__init__(self, LiteEthMACCRC32, description) - - -class LiteEthMACCRCChecker(Module): - """CRC Checker - - Check CRC at the end of each packet. - - Parameters - ---------- - description : description - description of the dataflow. - - Attributes - ---------- - sink : in - Packets input with CRC. - source : out - Packets output without CRC and "error" set to 0 - on eop when CRC OK / set to 1 when CRC KO. - """ - def __init__(self, crc_class, description): - self.sink = sink = Sink(description) - self.source = source = Source(description) - self.busy = Signal() - - # # # - - dw = flen(sink.data) - crc = crc_class(dw) - self.submodules += crc - ratio = crc.width//dw - - error = Signal() - fifo = InsertReset(SyncFIFO(description, ratio + 1)) - self.submodules += fifo - - fsm = FSM(reset_state="RESET") - self.submodules += fsm - - fifo_in = Signal() - fifo_out = Signal() - fifo_full = Signal() - - self.comb += [ - fifo_full.eq(fifo.fifo.level == ratio), - fifo_in.eq(sink.stb & (~fifo_full | fifo_out)), - fifo_out.eq(source.stb & source.ack), - - Record.connect(sink, fifo.sink), - fifo.sink.stb.eq(fifo_in), - self.sink.ack.eq(fifo_in), - - source.stb.eq(sink.stb & fifo_full), - source.sop.eq(fifo.source.sop), - source.eop.eq(sink.eop), - fifo.source.ack.eq(fifo_out), - source.payload.eq(fifo.source.payload), - - source.error.eq(sink.error | crc.error), - ] - - fsm.act("RESET", - crc.reset.eq(1), - fifo.reset.eq(1), - NextState("IDLE"), - ) - fsm.act("IDLE", - crc.data.eq(sink.data), - If(sink.stb & sink.sop & sink.ack, - crc.ce.eq(1), - NextState("COPY") - ) - ) - fsm.act("COPY", - crc.data.eq(sink.data), - If(sink.stb & sink.ack, - crc.ce.eq(1), - If(sink.eop, - NextState("RESET") - ) - ) - ) - self.comb += self.busy.eq(~fsm.ongoing("IDLE")) - - -class LiteEthMACCRC32Checker(LiteEthMACCRCChecker): - def __init__(self, description): - LiteEthMACCRCChecker.__init__(self, LiteEthMACCRC32, description) diff --git a/misoclib/com/liteeth/mac/core/gap.py b/misoclib/com/liteeth/mac/core/gap.py deleted file mode 100644 index c1bd9162..00000000 --- a/misoclib/com/liteeth/mac/core/gap.py +++ /dev/null @@ -1,27 +0,0 @@ -from misoclib.com.liteeth.common import * - -class LiteEthMACGap(Module): - def __init__(self, dw, ack_on_gap=False): - self.sink = sink = Sink(eth_phy_description(dw)) - self.source = source = Source(eth_phy_description(dw)) - - # # # - - gap = math.ceil(eth_interpacket_gap/(dw//8)) - self.submodules.counter = counter = Counter(max=gap) - - self.submodules.fsm = fsm = FSM(reset_state="COPY") - fsm.act("COPY", - counter.reset.eq(1), - Record.connect(sink, source), - If(sink.stb & sink.eop & sink.ack, - NextState("GAP") - ) - ) - fsm.act("GAP", - counter.ce.eq(1), - sink.ack.eq(int(ack_on_gap)), - If(counter.value == (gap-1), - NextState("COPY") - ) - ) diff --git a/misoclib/com/liteeth/mac/core/last_be.py b/misoclib/com/liteeth/mac/core/last_be.py deleted file mode 100644 index 42f7c641..00000000 --- a/misoclib/com/liteeth/mac/core/last_be.py +++ /dev/null @@ -1,43 +0,0 @@ -from misoclib.com.liteeth.common import * - - -class LiteEthMACTXLastBE(Module): - def __init__(self, dw): - self.sink = sink = Sink(eth_phy_description(dw)) - self.source = source = Source(eth_phy_description(dw)) - - # # # - - ongoing = Signal() - self.sync += \ - If(sink.stb & sink.ack, - If(sink.sop, - ongoing.eq(1) - ).Elif(sink.last_be, - ongoing.eq(0) - ) - ) - self.comb += [ - source.stb.eq(sink.stb & (sink.sop | ongoing)), - source.sop.eq(sink.sop), - source.eop.eq(sink.last_be), - source.data.eq(sink.data), - sink.ack.eq(source.ack) - ] - - -class LiteEthMACRXLastBE(Module): - def __init__(self, dw): - self.sink = sink = Sink(eth_phy_description(dw)) - self.source = source = Source(eth_phy_description(dw)) - - # # # - - self.comb += [ - source.stb.eq(sink.stb), - source.sop.eq(sink.sop), - source.eop.eq(sink.eop), - source.data.eq(sink.data), - source.last_be.eq(sink.eop), - sink.ack.eq(source.ack) - ] diff --git a/misoclib/com/liteeth/mac/core/padding.py b/misoclib/com/liteeth/mac/core/padding.py deleted file mode 100644 index 38b2a3da..00000000 --- a/misoclib/com/liteeth/mac/core/padding.py +++ /dev/null @@ -1,56 +0,0 @@ -from misoclib.com.liteeth.common import * - - -class LiteEthMACPaddingInserter(Module): - def __init__(self, dw, padding): - self.sink = sink = Sink(eth_phy_description(dw)) - self.source = source = Source(eth_phy_description(dw)) - - # # # - - padding_limit = math.ceil(padding/(dw/8))-1 - - self.submodules.counter = counter = Counter(16, reset=1) - counter_done = Signal() - self.comb += [ - counter.reset.eq(sink.stb & sink.sop & sink.ack), - counter.ce.eq(source.stb & source.ack), - counter_done.eq(counter.value >= padding_limit), - ] - - self.submodules.fsm = fsm = FSM(reset_state="IDLE") - fsm.act("IDLE", - Record.connect(sink, source), - If(source.stb & source.ack, - counter.ce.eq(1), - If(sink.eop, - If(~counter_done, - source.eop.eq(0), - NextState("PADDING") - ) - ) - ) - ) - fsm.act("PADDING", - source.stb.eq(1), - source.eop.eq(counter_done), - source.data.eq(0), - If(source.ack, - If(counter_done, - NextState("IDLE") - ) - ) - ) - - -class LiteEthMACPaddingChecker(Module): - def __init__(self, dw, packet_min_length): - self.sink = sink = Sink(eth_phy_description(dw)) - self.source = source = Source(eth_phy_description(dw)) - - # # # - - # XXX see if we should drop the packet when - # payload size < minimum ethernet payload size - self.comb += Record.connect(sink, source) - diff --git a/misoclib/com/liteeth/mac/core/preamble.py b/misoclib/com/liteeth/mac/core/preamble.py deleted file mode 100644 index 18e86f83..00000000 --- a/misoclib/com/liteeth/mac/core/preamble.py +++ /dev/null @@ -1,141 +0,0 @@ -from misoclib.com.liteeth.common import * - - -class LiteEthMACPreambleInserter(Module): - def __init__(self, dw): - self.sink = Sink(eth_phy_description(dw)) - self.source = Source(eth_phy_description(dw)) - - # # # - - preamble = Signal(64, reset=eth_preamble) - cnt_max = (64//dw)-1 - cnt = Signal(max=cnt_max+1) - clr_cnt = Signal() - inc_cnt = Signal() - - self.sync += \ - If(clr_cnt, - cnt.eq(0) - ).Elif(inc_cnt, - cnt.eq(cnt+1) - ) - - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - fsm.act("IDLE", - self.sink.ack.eq(1), - clr_cnt.eq(1), - If(self.sink.stb & self.sink.sop, - self.sink.ack.eq(0), - NextState("INSERT"), - ) - ) - fsm.act("INSERT", - self.source.stb.eq(1), - self.source.sop.eq(cnt == 0), - chooser(preamble, cnt, self.source.data), - If(cnt == cnt_max, - If(self.source.ack, NextState("COPY")) - ).Else( - inc_cnt.eq(self.source.ack) - ) - ) - fsm.act("COPY", - Record.connect(self.sink, self.source), - self.source.sop.eq(0), - - If(self.sink.stb & self.sink.eop & self.source.ack, - NextState("IDLE"), - ) - ) - - -class LiteEthMACPreambleChecker(Module): - def __init__(self, dw): - self.sink = Sink(eth_phy_description(dw)) - self.source = Source(eth_phy_description(dw)) - - # # # - - preamble = Signal(64, reset=eth_preamble) - cnt_max = (64//dw) - 1 - cnt = Signal(max=cnt_max+1) - clr_cnt = Signal() - inc_cnt = Signal() - - self.sync += \ - If(clr_cnt, - cnt.eq(0) - ).Elif(inc_cnt, - cnt.eq(cnt+1) - ) - - discard = Signal() - clr_discard = Signal() - set_discard = Signal() - - self.sync += \ - If(clr_discard, - discard.eq(0) - ).Elif(set_discard, - discard.eq(1) - ) - - sop = Signal() - clr_sop = Signal() - set_sop = Signal() - self.sync += \ - If(clr_sop, - sop.eq(0) - ).Elif(set_sop, - sop.eq(1) - ) - - ref = Signal(dw) - match = Signal() - self.comb += [ - chooser(preamble, cnt, ref), - match.eq(self.sink.data == ref) - ] - - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - - fsm.act("IDLE", - self.sink.ack.eq(1), - clr_cnt.eq(1), - clr_discard.eq(1), - If(self.sink.stb & self.sink.sop, - clr_cnt.eq(0), - inc_cnt.eq(1), - clr_discard.eq(0), - set_discard.eq(~match), - NextState("CHECK"), - ) - ) - fsm.act("CHECK", - self.sink.ack.eq(1), - If(self.sink.stb, - set_discard.eq(~match), - If(cnt == cnt_max, - If(discard | (~match), - NextState("IDLE") - ).Else( - set_sop.eq(1), - NextState("COPY") - ) - ).Else( - inc_cnt.eq(1) - ) - ) - ) - fsm.act("COPY", - Record.connect(self.sink, self.source), - self.source.sop.eq(sop), - clr_sop.eq(self.source.stb & self.source.ack), - - If(self.source.stb & self.source.eop & self.source.ack, - NextState("IDLE"), - ) - ) diff --git a/misoclib/com/liteeth/mac/frontend/__init__.py b/misoclib/com/liteeth/mac/frontend/__init__.py deleted file mode 100644 index e69de29b..00000000 diff --git a/misoclib/com/liteeth/mac/frontend/sram.py b/misoclib/com/liteeth/mac/frontend/sram.py deleted file mode 100644 index fc3d8c27..00000000 --- a/misoclib/com/liteeth/mac/frontend/sram.py +++ /dev/null @@ -1,234 +0,0 @@ -from misoclib.com.liteeth.common import * - -from migen.bank.description import * -from migen.bank.eventmanager import * - - -class LiteEthMACSRAMWriter(Module, AutoCSR): - def __init__(self, dw, depth, nslots=2): - self.sink = sink = Sink(eth_phy_description(dw)) - self.crc_error = Signal() - - slotbits = max(log2_int(nslots), 1) - lengthbits = log2_int(depth*4) # length in bytes - - self._slot = CSRStatus(slotbits) - self._length = CSRStatus(lengthbits) - - self.submodules.ev = EventManager() - self.ev.available = EventSourceLevel() - self.ev.finalize() - - # # # - - # packet dropped if no slot available - sink.ack.reset = 1 - - # length computation - increment = Signal(3) - self.comb += \ - If(sink.last_be[3], - increment.eq(1) - ).Elif(sink.last_be[2], - increment.eq(2) - ).Elif(sink.last_be[1], - increment.eq(3) - ).Else( - increment.eq(4) - ) - counter = Counter(lengthbits, increment=increment) - self.submodules += counter - - # slot computation - slot = Counter(slotbits) - self.submodules += slot - - ongoing = Signal() - - # status fifo - fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots) - self.submodules += fifo - - # fsm - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - - fsm.act("IDLE", - If(sink.stb & sink.sop, - If(fifo.sink.ack, - ongoing.eq(1), - counter.ce.eq(1), - NextState("WRITE") - ) - ) - ) - fsm.act("WRITE", - counter.ce.eq(sink.stb), - ongoing.eq(1), - If(sink.stb & sink.eop, - If((sink.error & sink.last_be) != 0, - NextState("DISCARD") - ).Else( - NextState("TERMINATE") - ) - ) - ) - fsm.act("DISCARD", - counter.reset.eq(1), - NextState("IDLE") - ) - self.comb += [ - fifo.sink.slot.eq(slot.value), - fifo.sink.length.eq(counter.value) - ] - fsm.act("TERMINATE", - counter.reset.eq(1), - slot.ce.eq(1), - fifo.sink.stb.eq(1), - NextState("IDLE") - ) - self.comb += [ - fifo.source.ack.eq(self.ev.available.clear), - self.ev.available.trigger.eq(fifo.source.stb), - self._slot.status.eq(fifo.source.slot), - self._length.status.eq(fifo.source.length), - ] - - # memory - mems = [None]*nslots - ports = [None]*nslots - for n in range(nslots): - mems[n] = Memory(dw, depth) - ports[n] = mems[n].get_port(write_capable=True) - self.specials += ports[n] - self.mems = mems - - cases = {} - for n, port in enumerate(ports): - cases[n] = [ - ports[n].adr.eq(counter.value[2:]), - ports[n].dat_w.eq(sink.data), - If(sink.stb & ongoing, - ports[n].we.eq(0xf) - ) - ] - self.comb += Case(slot.value, cases) - - -class LiteEthMACSRAMReader(Module, AutoCSR): - def __init__(self, dw, depth, nslots=2): - self.source = source = Source(eth_phy_description(dw)) - - slotbits = max(log2_int(nslots), 1) - lengthbits = log2_int(depth*4) # length in bytes - self.lengthbits = lengthbits - - self._start = CSR() - self._ready = CSRStatus() - self._slot = CSRStorage(slotbits) - self._length = CSRStorage(lengthbits) - - self.submodules.ev = EventManager() - self.ev.done = EventSourcePulse() - self.ev.finalize() - - # # # - - # command fifo - fifo = SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots) - self.submodules += fifo - self.comb += [ - fifo.sink.stb.eq(self._start.re), - fifo.sink.slot.eq(self._slot.storage), - fifo.sink.length.eq(self._length.storage), - self._ready.status.eq(fifo.sink.ack) - ] - - # length computation - self.submodules.counter = counter = Counter(lengthbits, increment=4) - - # fsm - first = Signal() - last = Signal() - last_d = Signal() - - fsm = FSM(reset_state="IDLE") - self.submodules += fsm - - fsm.act("IDLE", - counter.reset.eq(1), - If(fifo.source.stb, - NextState("CHECK") - ) - ) - fsm.act("CHECK", - If(~last_d, - NextState("SEND"), - ).Else( - NextState("END"), - ) - ) - length_lsb = fifo.source.length[0:2] - self.comb += [ - If(last, - If(length_lsb == 3, - source.last_be.eq(0b0010) - ).Elif(length_lsb == 2, - source.last_be.eq(0b0100) - ).Elif(length_lsb == 1, - source.last_be.eq(0b1000) - ).Else( - source.last_be.eq(0b0001) - ) - ) - ] - fsm.act("SEND", - source.stb.eq(1), - source.sop.eq(first), - source.eop.eq(last), - If(source.ack, - counter.ce.eq(~last), - NextState("CHECK") - ) - ) - fsm.act("END", - fifo.source.ack.eq(1), - self.ev.done.trigger.eq(1), - NextState("IDLE") - ) - - # first/last computation - self.sync += [ - If(fsm.ongoing("IDLE"), - first.eq(1) - ).Elif(source.stb & source.ack, - first.eq(0) - ) - ] - self.comb += last.eq((counter.value + 4) >= fifo.source.length) - self.sync += last_d.eq(last) - - # memory - rd_slot = fifo.source.slot - - mems = [None]*nslots - ports = [None]*nslots - for n in range(nslots): - mems[n] = Memory(dw, depth) - ports[n] = mems[n].get_port() - self.specials += ports[n] - self.mems = mems - - cases = {} - for n, port in enumerate(ports): - self.comb += ports[n].adr.eq(counter.value[2:]) - cases[n] = [source.data.eq(port.dat_r)] - self.comb += Case(rd_slot, cases) - - -class LiteEthMACSRAM(Module, AutoCSR): - def __init__(self, dw, depth, nrxslots, ntxslots): - self.submodules.writer = LiteEthMACSRAMWriter(dw, depth, nrxslots) - self.submodules.reader = LiteEthMACSRAMReader(dw, depth, ntxslots) - self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev) - self.sink, self.source = self.writer.sink, self.reader.source diff --git a/misoclib/com/liteeth/mac/frontend/wishbone.py b/misoclib/com/liteeth/mac/frontend/wishbone.py deleted file mode 100644 index 91c227f1..00000000 --- a/misoclib/com/liteeth/mac/frontend/wishbone.py +++ /dev/null @@ -1,41 +0,0 @@ -from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.mac.frontend import sram - -from migen.bus import wishbone -from migen.fhdl.simplify import FullMemoryWE - - -class LiteEthMACWishboneInterface(Module, AutoCSR): - def __init__(self, dw, nrxslots=2, ntxslots=2): - self.sink = Sink(eth_phy_description(dw)) - self.source = Source(eth_phy_description(dw)) - self.bus = wishbone.Interface() - - # # # - - # storage in SRAM - sram_depth = buffer_depth//(dw//8) - self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots) - self.comb += [ - Record.connect(self.sink, self.sram.sink), - Record.connect(self.sram.source, self.source) - ] - - # Wishbone interface - wb_rx_sram_ifs = [wishbone.SRAM(self.sram.writer.mems[n], read_only=True) - for n in range(nrxslots)] - # TODO: FullMemoryWE should move to Mibuild - wb_tx_sram_ifs = [FullMemoryWE()(wishbone.SRAM(self.sram.reader.mems[n], read_only=False)) - for n in range(ntxslots)] - wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs - - wb_slaves = [] - decoderoffset = log2_int(sram_depth) - decoderbits = log2_int(len(wb_sram_ifs)) - for n, wb_sram_if in enumerate(wb_sram_ifs): - def slave_filter(a, v=n): - return a[decoderoffset:decoderoffset+decoderbits] == v - wb_slaves.append((slave_filter, wb_sram_if.bus)) - self.submodules += wb_sram_if - wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True) - self.submodules += wb_con diff --git a/misoclib/com/liteeth/test/arp_tb.py b/misoclib/com/liteeth/test/arp_tb.py index f4b1fee4..08564502 100644 --- a/misoclib/com/liteeth/test/arp_tb.py +++ b/misoclib/com/liteeth/test/arp_tb.py @@ -4,7 +4,7 @@ from migen.bus.transactions import * from migen.sim.generic import run_simulation from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.mac import LiteEthMAC +from misoclib.com.liteeth.core.mac import LiteEthMAC from misoclib.com.liteeth.core.arp import LiteEthARP from misoclib.com.liteeth.test.common import * diff --git a/misoclib/com/liteeth/test/mac_core_tb.py b/misoclib/com/liteeth/test/mac_core_tb.py index c852417d..c7afdc29 100644 --- a/misoclib/com/liteeth/test/mac_core_tb.py +++ b/misoclib/com/liteeth/test/mac_core_tb.py @@ -4,7 +4,7 @@ from migen.bus.transactions import * from migen.sim.generic import run_simulation from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.mac.core import LiteEthMACCore +from misoclib.com.liteeth.core.mac.core import LiteEthMACCore from misoclib.com.liteeth.test.common import * from misoclib.com.liteeth.test.model import phy, mac diff --git a/misoclib/com/liteeth/test/mac_wishbone_tb.py b/misoclib/com/liteeth/test/mac_wishbone_tb.py index cfc1efdc..19e7b66d 100644 --- a/misoclib/com/liteeth/test/mac_wishbone_tb.py +++ b/misoclib/com/liteeth/test/mac_wishbone_tb.py @@ -4,7 +4,7 @@ from migen.bus.transactions import * from migen.sim.generic import run_simulation from misoclib.com.liteeth.common import * -from misoclib.com.liteeth.mac import LiteEthMAC +from misoclib.com.liteeth.core.mac import LiteEthMAC from misoclib.com.liteeth.test.common import * from misoclib.com.liteeth.test.model import phy, mac diff --git a/targets/kc705.py b/targets/kc705.py index 4cd792d6..8f65fa91 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -9,7 +9,7 @@ from misoclib.soc import mem_decoder from misoclib.soc.sdram import SDRAMSoC from misoclib.com.liteeth.phy import LiteEthPHY -from misoclib.com.liteeth.mac import LiteEthMAC +from misoclib.com.liteeth.core.mac import LiteEthMAC class _CRG(Module): diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 69ea8e7c..9e5eaf1b 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -15,7 +15,7 @@ from misoclib.soc import mem_decoder from misoclib.soc.sdram import SDRAMSoC from misoclib.com import gpio from misoclib.com.liteeth.phy import LiteEthPHY -from misoclib.com.liteeth.mac import LiteEthMAC +from misoclib.com.liteeth.core.mac import LiteEthMAC class _MXClockPads: diff --git a/targets/simple.py b/targets/simple.py index 62ea87ce..89bd57e2 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -4,7 +4,7 @@ from migen.genlib.io import CRG from misoclib.soc import SoC, mem_decoder from misoclib.com.liteeth.phy import LiteEthPHY -from misoclib.com.liteeth.mac import LiteEthMAC +from misoclib.com.liteeth.core.mac import LiteEthMAC class BaseSoC(SoC):