From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 22 Jul 2020 15:22:34 +0000 (+0200)
Subject: Handle rdly customization
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63dd35e9309d5418e725525a2d3d51ddd3d48aa9;p=gram.git

Handle rdly customization
---

diff --git a/examples/headless/main.c b/examples/headless/main.c
index 426f8f8..14cbfb7 100644
--- a/examples/headless/main.c
+++ b/examples/headless/main.c
@@ -100,6 +100,8 @@ int main(int argc, char *argv[]) {
 	const int kDumpWidth = 8;
 	size_t i;
 
+	struct gramProfile profile = {0,0};
+
 	if (argc != 3) {
 		fprintf(stderr, "Usage: %s port baudrate\n", argv[0]);
 		return EXIT_FAILURE;
@@ -117,6 +119,7 @@ int main(int argc, char *argv[]) {
 
 	printf("gram init... ");
 	gram_init(&ctx, (void*)0x10000000, (void*)0x00009000, (void*)0x00008000);
+	gram_load_calibration(&ctx, &profile);
 	printf("done\n");
 
 	srand(time(NULL));
diff --git a/libgram/include/gram.h b/libgram/include/gram.h
index aa1d9c0..7234465 100644
--- a/libgram/include/gram.h
+++ b/libgram/include/gram.h
@@ -24,9 +24,15 @@ struct gramCtx {
 	void *user_data;
 };
 
+struct gramProfile {
+	uint8_t rdly_p0;
+	uint8_t rdly_p1;
+};
+
 extern __attribute__((visibility ("default"))) int gram_init(struct gramCtx *ctx, void *ddr_base, void *core_base, void *phy_base);
 extern __attribute__((visibility ("default"))) int gram_memtest(struct gramCtx *ctx, size_t length, enum GramWidth width);
 extern __attribute__((visibility ("default"))) int gram_calibration_auto(struct gramCtx *ctx);
+extern __attribute__((visibility ("default"))) void gram_load_calibration(struct gramCtx *ctx, struct gramProfile *profile);
 
 #ifdef GRAM_RW_FUNC
 extern uint32_t gram_read(struct gramCtx *ctx, void *addr);
diff --git a/libgram/src/calibration.c b/libgram/src/calibration.c
index 1d29e47..7fd70fb 100644
--- a/libgram/src/calibration.c
+++ b/libgram/src/calibration.c
@@ -1,77 +1,75 @@
 #include <stdint.h>
+#include <stdio.h>
 
 #include "hw_regs.h"
 #include <gram.h>
 #include "dfii.h"
 #include "helpers.h"
 
-static void set_dly_sel(struct gramCtx *ctx, int sel) {
+static void set_rdly(struct gramCtx *ctx, unsigned int phase, unsigned int rdly) {
 #ifdef GRAM_RW_FUNC
-	gram_write(ctx, &(ctx->phy->dly_sel), sel);
+	if (phase == 0) {
+		gram_write(ctx, &(ctx->phy->rdly_p0), rdly);
+	} else if (phase == 1) {
+		gram_write(ctx, &(ctx->phy->rdly_p1), rdly);
+	}
 #else
-	ctx->phy->dly_sel = sel;
+	if (phase == 0) {
+		ctx->phy->rdly_p0 = rdly;
+	} else if (phase == 1) {
+		ctx->phy->rdly_p1 = rdly;
+	}
 #endif
 }
 
-static void rdly_dq_inc(struct gramCtx *ctx) {
+static void reset_burstdet(struct gramCtx *ctx) {
 #ifdef GRAM_RW_FUNC
-	gram_write(ctx, &(ctx->phy->rdly_dq_inc), 1);
+	gram_write(ctx, &(ctx->phy->burstdet), 0);
 #else
-	ctx->phy->rdly_dq_inc = 1;
+	ctx->phy->burstdet = 0;
 #endif
 }
 
-static void rdly_dq_bitslip_inc(struct gramCtx *ctx) {
+static bool read_burstdet(struct gramCtx *ctx, int phase) {
 #ifdef GRAM_RW_FUNC
-	gram_write(ctx, &(ctx->phy->rdly_dq_bitslip), 1);
+	return gram_read(ctx, &(ctx->phy->burstdet)) & (1 << phase);
 #else
-	ctx->phy->rdly_dq_bitslip = 1;
+	return ctx->phy->burstdet & (1 << phase);
 #endif
 }
 
-static void read_delay_inc(struct gramCtx *ctx, int module) {
-	/* sel module */
-	set_dly_sel(ctx, 1 << module);
-
-	/* inc delay */
-	rdly_dq_inc(ctx);
-
-	/* unsel module */
-	set_dly_sel(ctx, 0);
-
-	/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
-	set_dly_sel(ctx, 0xFF);
-	set_dly_sel(ctx, 0);
-}
-
-static void bitslip_inc(struct gramCtx *ctx, int module) {
-	/* sel module */
-	set_dly_sel(ctx, 1 << module);
-
-	/* inc delay */
-	rdly_dq_bitslip_inc(ctx);
+int gram_calibration_auto(struct gramCtx *ctx) {
+	uint32_t refval[8];
+	size_t i, j, k;
+	int score;
 
-	/* unsel module */
-	set_dly_sel(ctx, 0);
+	dfii_setsw(ctx, true);
 
-	/* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */
-	set_dly_sel(ctx, 0xFF);
-	set_dly_sel(ctx, 0);
-}
+	for (i = 0; i < 8; i++) {
+		for (j = 0; j < 8; j++) {
+			/* Generating test pattern */
+			for (k = 0; k < 8; k++) {
+				refval[k] = (0xABCD1234*i*j) & 0xFFFFFFFF;
+			}
 
-int gram_calibration_auto(struct gramCtx *ctx) {
-	dfii_setsw(ctx, true);
+			/* Writing to RAM */
 
-	// TODO: reset all delays and bitslip
+			/* Reading from RAM */
+			score = 0;
+			for (k = 0; k < 8; k++) {
 
-	read_delay_inc(ctx, 0);
-	read_delay_inc(ctx, 1);
+			}
+		}
+	}
 
 	dfii_setsw(ctx, false);
 
 	return 0;
 }
 
-void gram_load_calibration(void) {
-
+void gram_load_calibration(struct gramCtx *ctx, struct gramProfile *profile) {
+	dfii_setsw(ctx, true);
+	set_rdly(ctx, 0, profile->rdly_p0);
+	set_rdly(ctx, 1, profile->rdly_p1);
+	dfii_setsw(ctx, false);
 }
diff --git a/libgram/src/hw_regs.h b/libgram/src/hw_regs.h
index 6adb338..ac0457e 100644
--- a/libgram/src/hw_regs.h
+++ b/libgram/src/hw_regs.h
@@ -2,13 +2,9 @@
 #define HW_REGS_H
 
 struct gramPHYRegs {
-	uint32_t dly_sel;
-	uint32_t rdly_dq_rst;
-	uint32_t rdly_dq_inc;
-	uint32_t rdly_dq_bitslip_rst;
-	uint32_t rdly_dq_bitslip;
-	uint32_t burstdet_clr;
-	uint32_t burstdet_seen;
+	uint32_t burstdet;
+	uint32_t rdly_p0;
+	uint32_t rdly_p1;
 } __attribute__((packed));
 
 struct DFII_Phase {