From: lkcl <lkcl@web>
Date: Tue, 24 Aug 2021 16:43:06 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~311
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63e27d930a1ae81892468f18bd601d7657908d14;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index b5b0945e0..28db6bb06 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -147,6 +147,9 @@ behaviour. Given that Vertical-First steps through one element
 at a time, standard single (v3.0B) CTR decrementing should
 correspondingly be used.
 
+If CTR+VLSET Modes are requested, the amount that CTR is decremented
+by is the value of VL *after* truncation (should that occur).
+
 Note that, interestingly, due to the useful side-effects of `VLSET` mode
 it is actually useful to use Branch Conditional even
 to perform no actual branch operation, i.e to point to the instruction