From: lkcl <lkcl@web>
Date: Sat, 20 Nov 2021 14:51:12 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3365
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63e81b697988e9d37c1952cfa002a29abd3563da;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index bc63a5728..14c0ba0c3 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -15,7 +15,10 @@ These register files are required for POWER:
 
 Source code:
 
-* <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD>
+* register files: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;hb=HEAD>
+* core.py: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;hb=HEAD>
+* priority picker: <https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/picker.py;hb=HEAD>
+* all function units: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/compunits/compunits.py;hb=HEAD>
 
 For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.