From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 Feb 2020 17:11:47 +0000 (+0000)
Subject: add carry (not zeros, a Const of correct width)
X-Git-Tag: ls180-24jan2020~130
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63f0a7a495261a41b4cd0ed6a70f8c91beefc4b7;p=ieee754fpu.git

add carry (not zeros, a Const of correct width)
---

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 4a2e611b..ea1fa3a6 100644
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -117,7 +117,8 @@ class PartitionedSignal:
         return (pa.output, 0)
 
     def __lshift__(self, other):
-        result, _ = self.ls_op(self, other, carry=0)
+        z = Const(0, self.sig.shape())
+        result, _ = self.ls_op(self, other, carry=z) # TODO, carry
         return result
 
     def __rlshift__(self, other):