From: Benjamin Herrenschmidt Date: Tue, 9 Jun 2020 22:36:44 +0000 (+1000) Subject: litedram: Fix DRAM init mem using too many address bits X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63f10450a6e04d57c8cb3e11a9ddc7d7f95a21ac;p=microwatt.git litedram: Fix DRAM init mem using too many address bits Signed-off-by: Benjamin Herrenschmidt --- diff --git a/litedram/gen-src/dram-init-mem.vhdl b/litedram/gen-src/dram-init-mem.vhdl index 13bd0ce..a1b87d3 100644 --- a/litedram/gen-src/dram-init-mem.vhdl +++ b/litedram/gen-src/dram-init-mem.vhdl @@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is constant INIT_RAM_SIZE : integer := 16384; constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; - constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); constant INIT_RAM_FILE : string := "litedram_core.init"; type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); diff --git a/litedram/generated/arty/litedram-initmem.vhdl b/litedram/generated/arty/litedram-initmem.vhdl index 13bd0ce..a1b87d3 100644 --- a/litedram/generated/arty/litedram-initmem.vhdl +++ b/litedram/generated/arty/litedram-initmem.vhdl @@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is constant INIT_RAM_SIZE : integer := 16384; constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; - constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); constant INIT_RAM_FILE : string := "litedram_core.init"; type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); diff --git a/litedram/generated/nexys-video/litedram-initmem.vhdl b/litedram/generated/nexys-video/litedram-initmem.vhdl index 13bd0ce..a1b87d3 100644 --- a/litedram/generated/nexys-video/litedram-initmem.vhdl +++ b/litedram/generated/nexys-video/litedram-initmem.vhdl @@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is constant INIT_RAM_SIZE : integer := 16384; constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; - constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); constant INIT_RAM_FILE : string := "litedram_core.init"; type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); diff --git a/litedram/generated/sim/litedram-initmem.vhdl b/litedram/generated/sim/litedram-initmem.vhdl index 7abaf48..b6886f9 100644 --- a/litedram/generated/sim/litedram-initmem.vhdl +++ b/litedram/generated/sim/litedram-initmem.vhdl @@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is constant INIT_RAM_SIZE : integer := 16384; constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; - constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); + constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1); constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init"; type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);