From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 17 Jun 2019 20:19:45 +0000 (-0700)
Subject: Copy not move parameters/attributes
X-Git-Tag: working-ls180~1237^2~94
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=63fc879a5f698803d563a57275cc99a3df2d1414;p=yosys.git

Copy not move parameters/attributes
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 9c4e6bb39..184fbfaee 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -599,11 +599,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 			if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
                         RTLIL::Cell *existing_cell = module->cell(c->name);
                         if (existing_cell) {
-                                cell->parameters = std::move(existing_cell->parameters);
-                                cell->attributes = std::move(existing_cell->attributes);
+                                cell->parameters = existing_cell->parameters;
+                                cell->attributes = existing_cell->attributes;
                         }
                         else {
-                                cell->parameters = std::move(c->parameters);
+                                cell->parameters = c->parameters;
+                                cell->attributes = c->attributes;
                         }
 			for (auto &conn : c->connections()) {
 				RTLIL::SigSpec newsig;