From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Apr 2020 10:24:23 +0000 (+0100)
Subject: success using SelectableInt in cnttzd test
X-Git-Tag: div_pipeline~1572
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6415a75f121bf6bcc35c19fba1f5efe396bf065d;p=soc.git

success using SelectableInt in cnttzd test
---

diff --git a/src/soc/decoder/helpers.py b/src/soc/decoder/helpers.py
index 4c595ca9..941bcbc8 100644
--- a/src/soc/decoder/helpers.py
+++ b/src/soc/decoder/helpers.py
@@ -1,4 +1,5 @@
 import unittest
+from soc.decoder.selectable_int import SelectableInt
 
 
 def exts(value, bits):
@@ -7,11 +8,15 @@ def exts(value, bits):
 
 
 def EXTS64(value):
-    return exts(value, 32) & ((1 << 64)-1)
+    if isinstance(value, SelectableInt):
+        value = value.value
+    return SelectableInt(exts(value, 32) & ((1 << 64)-1), 64)
 
 
 def EXTZ64(value):
-    return value & ((1<<32)-1)
+    if isinstance(value, SelectableInt):
+        value = value.value
+    return SelectableInt(value & ((1<<32)-1), 64)
 
 def rotl(value, bits, wordlen):
     mask = (1 << wordlen) - 1
diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py
index 36a7022e..eb71052c 100644
--- a/src/soc/decoder/power_pseudo.py
+++ b/src/soc/decoder/power_pseudo.py
@@ -19,6 +19,7 @@ from nmigen.back.pysim import Simulator, Delay
 from nmigen import Module, Signal
 
 from soc.decoder.pseudo.parser import GardenSnakeCompiler
+from soc.decoder.selectable_int import SelectableInt
 
 ####### Test code #######
 
@@ -53,9 +54,9 @@ RA <- [0]*56|| perm[0:7]
 cnttzd = """
 n  <- 0
 do while n < 64
-   if (RS)[63-n] = 0b1 then
+    if (RS)[63-n] = 0b1 then
         leave
-   n  <- n + 1
+    n  <- n + 1
 RA <- EXTZ64(n)
 print (RA)
 """
@@ -73,8 +74,7 @@ def tolist(num):
 
 
 def get_reg_hex(reg):
-    report = ''.join(map(str, reg))
-    return hex(int('0b%s' % report, 2))
+    return hex(reg.value)
 
 
 class GPR(dict):
@@ -83,7 +83,7 @@ class GPR(dict):
         self.sd = sd
         self.regfile = regfile
         for i in range(32):
-            self[i] = [0] * 64 # TODO: needs to be IntClass(value=0, len=64)
+            self[i] = SelectableInt(0, 64)
 
     def set_form(self, form):
         self.form = form
@@ -194,7 +194,7 @@ def test():
                 reg = getform[wname]
                 print ("write regs", wname, d[wname], reg)
                 regidx = yield reg
-                gsc.gpr[regidx] = tolist(d[wname])
+                gsc.gpr[regidx] = d[wname]
 
     sim.add_process(process)
     with sim.write_vcd("simulator.vcd", "simulator.gtkw",
diff --git a/src/soc/decoder/pseudo/lexer.py b/src/soc/decoder/pseudo/lexer.py
index 82578ac9..e2ba0a2b 100644
--- a/src/soc/decoder/pseudo/lexer.py
+++ b/src/soc/decoder/pseudo/lexer.py
@@ -276,7 +276,8 @@ class PowerLexer:
 
     def t_STRING(self, t):
         r"'([^\\']+|\\'|\\\\)*'"  # I think this is right ...
-        t.value=t.value[1:-1].decode("string-escape") # .swapcase() # for fun
+        print (repr(t.value))
+        t.value=t.value[1:-1]
         return t
 
     t_COLON = r':'
diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 8ef80a46..a73ceb5d 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -39,7 +39,7 @@ class SelectableInt:
 
     def __getitem__(self, key):
         if isinstance(key, int):
-            assert key < self.bits
+            assert key < self.bits, "key %d accessing %d" % (key, self.bits)
             assert key >= 0
             key = self.bits - (key + 1)