From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 21 Oct 2015 13:42:50 +0000 (+0200)
Subject: Improved inout handling in equiv_make
X-Git-Tag: yosys-0.6~101
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6416dfee9380c03f9391784d885caebfed0072b4;p=yosys.git

Improved inout handling in equiv_make
---

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index c001fdbfe..8b063c542 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -280,7 +280,7 @@ struct EquivMakeWorker
 
 		for (auto c : cells_list)
 		for (auto &conn : c->connections())
-			if (ct.cell_input(c->type, conn.first)) {
+			if (!ct.cell_output(c->type, conn.first)) {
 				SigSpec old_sig = assign_map(conn.second);
 				SigSpec new_sig = rd_signal_map(old_sig);
 				if (old_sig != new_sig) {