From: lkcl <lkcl@web>
Date: Mon, 14 Dec 2020 04:03:23 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1327
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64216baaff4390f6baf0a82f155423081bcf993a;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 6c0646eb1..5d7059d4f 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -92,6 +92,23 @@ SV Registers are numbered using the notation `SV[F]R<N>_<M>` where `<N>` is a de
 
 ## Integer Registers
 
+setvli ..., VL=7
+add r20, r25, r30, elwidth=64, subvl=1
+
+where r20, r25, and r30 are standard OpenPower register names.
+Those names correspond to SVR20_00, SVR25_00, and SVR30_00.
+
+pseudocode:
+const STD_TO_SV_SHIFT = 2; // gets bigger as reg files expand to 256, 512,
+... registers
+
+VL=7 // setvli (omitting maxvl here)
+
+for(i=0;i<VL;i++) {
+    regs[(20 << STD_TO_SV_SHIFT) + i] = regs[(25 << STD_TO_SV_SHIFT) + i]
+        + regs[(30 << STD_TO_SV_SHIFT) + i];
+}
+
 Standard PowerISA Integer registers are aliased to some of the SV integer registers:
 
 | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register | Integer<br/>Register | SV Integer<br/>Register |