From: Luke Kenneth Casson Leighton Date: Sat, 10 Sep 2022 11:48:03 +0000 (+0100) Subject: hyperlink to SVP64-Single X-Git-Tag: opf_rfc_ls005_v1~523 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64222ae70ecd9289f86883fa74171fb5330576d2;p=libreriscv.git hyperlink to SVP64-Single --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index c17a2022b..00e8fdc9a 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -312,7 +312,8 @@ Scheme. * **0000** - all 24 bits bits 8-31 are zero (0x000000) * **!zero** - bits 8-31 may be any value *other* than zero (0x000001-0xffffff) * **nnnn** - bits 8-31 may be any value in the range 0x000000 to 0xffffff -* **SVP64Single** - a (TBD) Encoding that is near-identical to SVP64 +* **SVP64Single** - a ([TBD](https://bugs.libre-soc.org/show_bug.cgi?id=905)) + Encoding that is near-identical to SVP64 except that it is not a Vector Operation (equivalent to hard-coded VL=1 at all times). Predication is permitted, Element-width-overrides is permitted, Saturation is permitted. SVP64Single is a **scalar** augmentation