From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 29 Sep 2022 18:00:30 +0000 (+0100)
Subject: sv.adde not sv.addeo
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6430e32bd81bd37403d0e7601e4cec39cf26b8cd;p=openpower-isa.git

sv.adde not sv.addeo
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bigint.py b/src/openpower/decoder/isa/test_caller_svp64_bigint.py
index fc1f420c..d14bf8e1 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_bigint.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bigint.py
@@ -34,7 +34,7 @@ class DecoderTestCase(FHDLTestCase):
         r5/r4: 0x8000_0000_0000_0000 0x0000_0000_0000_0001 =
         r1/r0: 0x8000_0000_0000_0002 0x0000_0000_0000_0000
         """
-        isa = SVP64Asm(['sv.addeo *0, *2, *4'
+        isa = SVP64Asm(['sv.adde *0, *2, *4'
                        ])
         lst = list(isa)
         print ("listing", lst)