From: Luke Kenneth Casson Leighton Date: Sun, 2 Jan 2022 16:15:27 +0000 (+0000) Subject: add SIM_BRAM_CHAINBOOT parameter to SYSCON X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6431824a5f37a3a3d729d407b43f1443de93ff98;p=microwatt.git add SIM_BRAM_CHAINBOOT parameter to SYSCON this allows the mini-BIOS to jump to a specific address rather than always jump to 0x0 --- diff --git a/Makefile b/Makefile index 7d0d320..9ea90b5 100644 --- a/Makefile +++ b/Makefile @@ -145,9 +145,10 @@ RAM_INIT_FILE=hello_world/hello_world.hex #RAM_INIT_FILE=micropython/firmware.hex # Linux -#MEMORY_SIZE=16777216 # 268435456 +#MEMORY_SIZE=536870912 #RAM_INIT_FILE=dtbImage.microwatt.hex -SIM_MAIN_BRAM=false +#SIM_MAIN_BRAM=false +#SIM_BRAM_CHAINBOOT=5242880 # 0x500000 FPGA_TARGET ?= ORANGE-CRAB @@ -177,7 +178,7 @@ endif GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \ -gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) \ - -gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) + -gSIM_MAIN_BRAM=$(SIM_MAIN_BRAM) -gSIM_BRAM_CHAINBOOT=$(SIM_BRAM_CHAINBOOT) clkgen=fpga/clk_gen_ecp5.vhd diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl index 70f938e..98ebeb2 100644 --- a/fpga/top-generic.vhdl +++ b/fpga/top-generic.vhdl @@ -11,6 +11,7 @@ entity toplevel is RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; SIM_MAIN_BRAM : boolean := false; + SIM_BRAM_CHAINBOOT : positive := 0; CLK_INPUT : positive := 100000000; CLK_FREQUENCY : positive := 100000000; HAS_FPU : boolean := true; @@ -79,6 +80,7 @@ begin soc0: entity work.soc generic map( MEMORY_SIZE => MEMORY_SIZE, + SIM_BRAM_CHAINBOOT => SIM_BRAM_CHAINBOOT, SIM_MAIN_BRAM => SIM_MAIN_BRAM, RAM_INIT_FILE => RAM_INIT_FILE, SIM => false, diff --git a/soc.vhdl b/soc.vhdl index d72a009..1c3599e 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -58,6 +58,7 @@ entity soc is DISABLE_FLATTEN_CORE : boolean := false; HAS_DRAM : boolean := false; SIM_MAIN_BRAM : boolean := false; + SIM_BRAM_CHAINBOOT : positive := 0; DRAM_SIZE : integer := 0; RESET_ADDRESS : std_ulogic_vector(63 downto 0) := (others => '0'); -- hack to jump-start alternative (e.g. verilator-loaded linux kernel) @@ -646,6 +647,7 @@ begin BRAM_SIZE => MEMORY_SIZE, DRAM_SIZE => DRAM_SIZE, DRAM_INIT_SIZE => DRAM_INIT_SIZE, + SIM_BRAM_CHAINBOOT => SIM_BRAM_CHAINBOOT, CLK_FREQ => CLK_FREQ, HAS_SPI_FLASH => HAS_SPI_FLASH, SPI_FLASH_OFFSET => SPI_FLASH_OFFSET, diff --git a/syscon.vhdl b/syscon.vhdl index 31d8d0a..8fa8ae9 100644 --- a/syscon.vhdl +++ b/syscon.vhdl @@ -12,6 +12,7 @@ entity syscon is CLK_FREQ : integer; HAS_UART : boolean; HAS_DRAM : boolean; + SIM_BRAM_CHAINBOOT : integer; BRAM_SIZE : integer; DRAM_SIZE : integer; DRAM_INIT_SIZE : integer; @@ -52,6 +53,7 @@ architecture behaviour of syscon is constant SYS_REG_SPIFLASHINFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "000111"; constant SYS_REG_UART0_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001000"; constant SYS_REG_UART1_INFO : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001001"; + constant SYS_REG_BRAM_BOOTADDR : std_ulogic_vector(SYS_REG_BITS-1 downto 0) := "001010"; -- Muxed reg read signal signal reg_out : std_ulogic_vector(63 downto 0); @@ -112,6 +114,7 @@ architecture behaviour of syscon is signal info_fl_off : std_ulogic_vector(31 downto 0); signal uinfo_16550 : std_ulogic; signal uinfo_freq : std_ulogic_vector(31 downto 0); + signal reg_brambootaddr : std_ulogic_vector(63 downto 0); -- Wishbone response latch signal wb_rsp : wb_io_slave_out; @@ -139,6 +142,7 @@ begin SYS_REG_INFO_HAS_URT1 => info_has_urt1, others => '0'); + reg_brambootaddr <= std_ulogic_vector(to_unsigned(SIM_BRAM_CHAINBOOT, 64)); reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52)); reg_draminfo <= x"000" & std_ulogic_vector(to_unsigned(DRAM_SIZE, 52)) when HAS_DRAM else (others => '0'); @@ -177,6 +181,7 @@ begin reg_spiinfo when SYS_REG_SPIFLASHINFO, reg_uart0info when SYS_REG_UART0_INFO, reg_uart1info when SYS_REG_UART1_INFO, + reg_brambootaddr when SYS_REG_BRAM_BOOTADDR, (others => '0') when others; wb_rsp.dat <= reg_out(63 downto 32) when wishbone_in.adr(2) = '1' else reg_out(31 downto 0);