From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Feb 2022 00:41:59 +0000 (+0000)
Subject: add interrupt controller module, remove stall feature from CPU buses
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6439e0f6a8e3a17bfe3b865a532e6d2ca51fc108;p=ls2.git

add interrupt controller module, remove stall feature from CPU buses
---

diff --git a/src/ls2.py b/src/ls2.py
index 23a1d77..14cad43 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -68,9 +68,9 @@ class DDR3SoC(SoC, Elaboratable):
         # set up CPU, with 64-to-32-bit downconverters
         self.cpu = ExternalCore(name="ext_core")
         cvtdbus = wishbone.Interface(addr_width=30, data_width=32,
-                                     features={'stall'}, granularity=8)
+                                     granularity=8)
         cvtibus = wishbone.Interface(addr_width=30, data_width=32,
-                                     features={'stall'}, granularity=8)
+                                     granularity=8)
         self.dbusdowncvt = WishboneDownConvert(self.cpu.dbus, cvtdbus)
         self.ibusdowncvt = WishboneDownConvert(self.cpu.ibus, cvtibus)
         self._arbiter.add(cvtibus) # I-Cache Master
@@ -138,9 +138,6 @@ class DDR3SoC(SoC, Elaboratable):
             m.submodules.bootmem = self.bootmem
         m.submodules.ram = self.ram
         m.submodules.uart = self.uart
-        if False:
-            m.submodules.intc = self.intc
-            m.submodules.cpu = self.cpu
         m.submodules.arbiter = self._arbiter
         m.submodules.decoder = self._decoder
         if hasattr(self, "ddrphy"):
@@ -148,6 +145,7 @@ class DDR3SoC(SoC, Elaboratable):
             m.submodules.dramcore = self.dramcore
             m.submodules.drambone = self.drambone
         if hasattr(self, "cpu"):
+            m.submodules.intc = self.intc
             m.submodules.extcore = self.cpu
             m.submodules.dbuscvt = self.dbusdowncvt
             m.submodules.ibuscvt = self.ibusdowncvt