From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 8 Jun 2019 13:39:09 +0000 (+0100)
Subject: convert Reg_Rsv and rest of FU_Reg Matrix to variable n_src
X-Git-Tag: div_pipeline~1869
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=643c827100784d80f6ec39e1013a398dc7568895;p=soc.git

convert Reg_Rsv and rest of FU_Reg Matrix to variable n_src
---

diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py
index cd454f8e..bac2ea33 100644
--- a/src/scoreboard/fu_reg_matrix.py
+++ b/src/scoreboard/fu_reg_matrix.py
@@ -90,7 +90,8 @@ class FURegDepMatrix(Elaboratable):
         # ---
         # array of Register Reservation vectors
         # ---
-        regrsv = Array(Reg_Rsv(self.n_fu_row) for r in range(self.n_reg_col))
+        regrsv = Array(Reg_Rsv(self.n_fu_row, self.n_src) \
+                        for r in range(self.n_reg_col))
         for rn in range(self.n_reg_col):
             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
 
@@ -117,6 +118,7 @@ class FURegDepMatrix(Elaboratable):
         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 
+        # same for src
         for i in range(self.n_src):
             rd_src_pend = []
             for fu in range(self.n_fu_row):
@@ -138,33 +140,39 @@ class FURegDepMatrix(Elaboratable):
         # connect Reg Selection vector
         # ---
         dest_rsel = []
-        src1_rsel = []
-        src2_rsel = []
         for rn in range(self.n_reg_col):
             rsv = regrsv[rn]
             dest_rsel_o = []
-            src1_rsel_o = []
-            src2_rsel_o = []
             for fu in range(self.n_fu_row):
                 dc = dm[fu]
                 # accumulate cell reg-select outputs dest/src1/src2
                 dest_rsel_o.append(dc.dest_rsel_o[rn])
-                src1_rsel_o.append(dc.src_rsel_o[0][rn])
-                src2_rsel_o.append(dc.src_rsel_o[1][rn])
             # connect cell reg-select outputs to Reg Vector In
-            m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
-                         rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
-                         rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
-                        ]
+            m.d.comb += rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
+
             # accumulate Reg-Sel Vector outputs
             dest_rsel.append(rsv.dest_rsel_o)
-            src1_rsel.append(rsv.src1_rsel_o)
-            src2_rsel.append(rsv.src2_rsel_o)
 
         # ... and output them from this module (horizontal, width=REGs)
         m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
-        m.d.comb += self.src_rsel_o[0].eq(Cat(*src1_rsel))
-        m.d.comb += self.src_rsel_o[1].eq(Cat(*src2_rsel))
+
+        # same for src
+        for i in range(self.n_src):
+            src_rsel = []
+            for rn in range(self.n_reg_col):
+                rsv = regrsv[rn]
+                src_rsel_o = []
+                for fu in range(self.n_fu_row):
+                    dc = dm[fu]
+                    # accumulate cell reg-select outputs dest/src1/src2
+                    src_rsel_o.append(dc.src_rsel_o[i][rn])
+                # connect cell reg-select outputs to Reg Vector In
+                m.d.comb += rsv.src_rsel_i[i].eq(Cat(*src_rsel_o)),
+                # accumulate Reg-Sel Vector outputs
+                src_rsel.append(rsv.src_rsel_o[i])
+
+            # ... and output them from this module (horizontal, width=REGs)
+            m.d.comb += self.src_rsel_o[i].eq(Cat(*src_rsel))
 
         # ---
         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
diff --git a/src/scoreboard/reg_select.py b/src/scoreboard/reg_select.py
index eca3328e..3919cce3 100644
--- a/src/scoreboard/reg_select.py
+++ b/src/scoreboard/reg_select.py
@@ -1,23 +1,24 @@
-from nmigen import Elaboratable, Module, Signal
+from nmigen import Elaboratable, Module, Signal, Array
 
 
 class Reg_Rsv(Elaboratable):
     """ these are allocated per-Register (vertically),
         and are each of length fu_count
     """
-    def __init__(self, fu_count):
+    def __init__(self, fu_count, n_src):
+        self.n_src = n_src
         self.fu_count = fu_count
         self.dest_rsel_i = Signal(fu_count, reset_less=True)
-        self.src1_rsel_i = Signal(fu_count, reset_less=True)
-        self.src2_rsel_i = Signal(fu_count, reset_less=True)
+        self.src_rsel_i = Array(Signal(fu_count, name="src_rsel_i",
+                                       reset_less=True) \
+                                for i in range(n_src))
         self.dest_rsel_o = Signal(reset_less=True)
-        self.src1_rsel_o = Signal(reset_less=True)
-        self.src2_rsel_o = Signal(reset_less=True)
+        self.src_rsel_o = Signal(n_src, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
         m.d.comb += self.dest_rsel_o.eq(self.dest_rsel_i.bool())
-        m.d.comb += self.src1_rsel_o.eq(self.src1_rsel_i.bool())
-        m.d.comb += self.src2_rsel_o.eq(self.src2_rsel_i.bool())
+        for i in range(self.n_src):
+            m.d.comb += self.src_rsel_o[i].eq(self.src_rsel_i[i].bool())
         return m