From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 6 Dec 2018 06:29:21 +0000 (+0100)
Subject: Bugfix in opt_expr handling of a<0 and a>=0
X-Git-Tag: yosys-0.9~392
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=643f858acffcb40cce4686a5a039dc80c18b933d;p=yosys.git

Bugfix in opt_expr handling of a<0 and a>=0

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 0ba233c62..610edc5e9 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1406,7 +1406,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
 			{
 				if (sigConst.is_fully_zero()) {
-					RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
+					RTLIL::SigSpec a_prime(RTLIL::State::S0, GetSize(cell->getPort("\\Y")));
 					if (is_lt) {
 						log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
 								log_id(cell->type), log_id(cell));