From: Alberto Gonzalez Date: Sun, 19 Apr 2020 22:32:28 +0000 (+0000) Subject: Replace `std::map` with `dict` for `celltypeMap`. X-Git-Tag: working-ls180~517^2~19 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=644e55b3d30159b3dc033e5cfbfe07bde2604ea7;p=yosys.git Replace `std::map` with `dict` for `celltypeMap`. --- diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 55d80bad1..416d96862 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -464,7 +464,7 @@ struct TechmapWorker } bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, pool &handled_cells, - const std::map> &celltypeMap, bool in_recursion) + const dict> &celltypeMap, bool in_recursion) { std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping"; @@ -1300,7 +1300,7 @@ struct TechmapPass : public Pass { log_header(design, "Continuing TECHMAP pass.\n"); - std::map> celltypeMap; + dict> celltypeMap; for (auto module : map->modules()) { if (module->attributes.count(ID::techmap_celltype) && !module->attributes.at(ID::techmap_celltype).bits.empty()) { char *p = strdup(module->attributes.at(ID::techmap_celltype).decode_string().c_str()); @@ -1381,7 +1381,7 @@ struct FlattenPass : public Pass { extra_args(args, argidx, design); - std::map> celltypeMap; + dict> celltypeMap; for (auto module : design->modules()) celltypeMap[module->name].insert(module->name);