From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 6 Dec 2006 10:54:16 +0000 (-0500)
Subject: Added in endianness conversion on memory accesses as the data goes out. This will... 
X-Git-Tag: m5_2.0_beta3~274^2~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6456cb535cce8b35c36fa0366fc8766ecffbbf44;p=gem5.git

Added in endianness conversion on memory accesses as the data goes out. This will break the checker!

--HG--
extra : convert_revision : b8191cab09ab8f3ced05693293f058382319ed8e
---

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 4facea9f9..379724166 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -596,7 +596,11 @@ LSQUnit<Impl>::writebackStores()
 
         assert(!inst->memData);
         inst->memData = new uint8_t[64];
-        memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data,
+
+        TheISA::IntReg convertedData =
+            TheISA::htog(storeQueue[storeWBIdx].data);
+
+        memcpy(inst->memData, (uint8_t *)&convertedData,
                req->getSize());
 
         PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);