From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 4 Jul 2014 08:29:42 +0000 (+0200)
Subject: Upgrade mor1kx. This fixes the UART bug that was due to IRQ 0 and 1 being non-maskable.
X-Git-Tag: 24jan2021_ls180~2700
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6462ee7fe198b197a5352cd09c74d6ea0f19ead6;p=litex.git

Upgrade mor1kx. This fixes the UART bug that was due to IRQ 0 and 1 being non-maskable.
---

diff --git a/verilog/mor1kx/submodule b/verilog/mor1kx/submodule
index e0e2f058..bae88d1b 160000
--- a/verilog/mor1kx/submodule
+++ b/verilog/mor1kx/submodule
@@ -1 +1 @@
-Subproject commit e0e2f058e3ebba40a9a0231c5f54aa1d6b04bb74
+Subproject commit bae88d1bbc3f0dd12aacb9d119902b4a0c5a7e1b