From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 9 Mar 2020 20:22:27 +0000 (+0000)
Subject: disable transparent=False for now
X-Git-Tag: div_pipeline~1737
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64806776581720bc8e92e0c2d0aa087e5910d345;p=soc.git

disable transparent=False for now
---

diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index 853e2c80..eebd16e0 100644
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -277,7 +277,7 @@ class LDSTCompUnit(Elaboratable):
             rdport = self.mem.rdport
             comb += rdport.addr.eq(self.addr_o)
             comb += self.data_o.eq(rdport.data)
-            comb += rdport.en.eq(1)
+            # comb += rdport.en.eq(1) # only when transparent=False
 
         return m
 
diff --git a/src/soc/experiment/testmem.py b/src/soc/experiment/testmem.py
index 72b1a283..05101d0e 100644
--- a/src/soc/experiment/testmem.py
+++ b/src/soc/experiment/testmem.py
@@ -6,7 +6,7 @@ class TestMemory(Elaboratable):
         self.ddepth = 1 # regwid //8
         depth = (1<<addrw) // self.ddepth
         self.mem   = Memory(width=regwid, depth=depth, init=range(0, depth))
-        self.rdport = self.mem.read_port(transparent=False)
+        self.rdport = self.mem.read_port() # not now transparent=False)
         self.wrport = self.mem.write_port()
 
     def elaborate(self, platform):