From: Kewen Lin Date: Fri, 1 Nov 2019 14:08:50 +0000 (+0000) Subject: [rs6000] vector conversion RTL pattern update for diff unit size X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6485d5d69a71d2c93b8f97fa899cb906628d3a5f;p=gcc.git [rs6000] vector conversion RTL pattern update for diff unit size 2019-11-01 Kewen Lin * config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes. * config/rs6000/vsx.md (UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove. (vsx_xvcvspdp): New define_expand, old define_insn split to... (vsx_xvcvspdp_be): ... this. New. And... (vsx_xvcvspdp_le): ... this. New. (vsx_xvcvxwdp): New define_expand, old define_insn split to... (vsx_xvcvxwdp_be): ... this. New. And... (vsx_xvcvxwdp_le): ... this. New. (vsx_xvcvspxds): New define_expand, old define_insn split to... (vsx_xvcvspxds_be): ... this. New. And... (vsx_xvcvspxds_le): ... this. New. From-SVN: r277709 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1a39d85d8f9..bb7819e1fea 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2019-11-01 Kewen Lin + + * config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes. + * config/rs6000/vsx.md (UNSPEC_VSX_CVSPSXDS, + UNSPEC_VSX_CVSPUXDS): Remove. + (vsx_xvcvspdp): New define_expand, old define_insn split to... + (vsx_xvcvspdp_be): ... this. New. And... + (vsx_xvcvspdp_le): ... this. New. + (vsx_xvcvxwdp): New define_expand, old define_insn split to... + (vsx_xvcvxwdp_be): ... this. New. And... + (vsx_xvcvxwdp_le): ... this. New. + (vsx_xvcvspxds): New define_expand, old define_insn split to... + (vsx_xvcvspxds_be): ... this. New. And... + (vsx_xvcvspxds_le): ... this. New. + 2019-11-01 Kewen Lin * config/rs6000/vsx.md (UNSPEC_VSX_CVSXWSP, UNSPEC_VSX_CVUXWSP, diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index 677062cb7e9..2051358133d 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -74,6 +74,10 @@ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ +/* Half VMX/VSX vector (for internal use) */ +VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ +VECTOR_MODE (INT, SI, 2); /* V2SI */ + /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 05fcdd6cfc0..fc61ae1e7b3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -275,8 +275,6 @@ UNSPEC_VSX_CVUXWDP UNSPEC_VSX_CVSXDSP UNSPEC_VSX_CVUXDSP - UNSPEC_VSX_CVSPSXDS - UNSPEC_VSX_CVSPUXDS UNSPEC_VSX_FLOAT2 UNSPEC_VSX_UNS_FLOAT2 UNSPEC_VSX_FLOATE @@ -2114,14 +2112,36 @@ "xscvdpsp %x0,%x1" [(set_attr "type" "fp")]) -(define_insn "vsx_xvcvspdp" +(define_insn "vsx_xvcvspdp_be" [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (V4SFmode)" + (float_extend:V2DF + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN" + "xvcvspdp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_insn "vsx_xvcvspdp_le" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa") + (float_extend:V2DF + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN" "xvcvspdp %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_expand "vsx_xvcvspdp" + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V4SF 1 "vsx_register_operand")] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvspdp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvspdp_le (operands[0], operands[1])); + DONE; +}) + (define_insn "vsx_xvcvdpsp" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa") (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "v,wa")] @@ -2341,16 +2361,39 @@ "xvcvuxdsp %x0,%x1" [(set_attr "type" "vecdouble")]) -;; Convert from 32-bit to 64-bit types -;; Provide both vector and scalar targets -(define_insn "vsx_xvcvsxwdp" +;; Convert vector of 32-bit signed/unsigned integers to vector of +;; 64-bit floating point numbers. +(define_insn "vsx_xvcvxwdp_be" [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSXWDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvsxwdp %x0,%x1" + (any_float:V2DF + (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_insn "vsx_xvcvxwdp_le" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (any_float:V2DF + (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvxwdp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvxwdp" + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V4SI 1 "vsx_register_operand") + (any_float (pc))] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvxwdp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvxwdp_le (operands[0], operands[1])); + DONE; +}) + (define_insn "vsx_xvcvsxwdp_df" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") (unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] @@ -2359,14 +2402,6 @@ "xvcvsxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvuxwdp" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVUXWDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvuxwdp %x0,%x1" - [(set_attr "type" "vecdouble")]) - (define_insn "vsx_xvcvuxwdp_df" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") (unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] @@ -2375,22 +2410,39 @@ "xvcvuxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvspsxds" +;; Convert vector of 32-bit floating point numbers to vector of +;; 64-bit signed/unsigned integers. +(define_insn "vsx_xvcvspxds_be" [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPSXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvspsxds %x0,%x1" + (any_fix:V2DI + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvspxds %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvspuxds" +(define_insn "vsx_xvcvspxds_le" [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPUXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvspuxds %x0,%x1" + (any_fix:V2DI + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvspxds %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_expand "vsx_xvcvspxds" + [(match_operand:V2DI 0 "vsx_register_operand") + (match_operand:V4SF 1 "vsx_register_operand") + (any_fix (pc))] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvspxds_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvspxds_le (operands[0], operands[1])); + DONE; +}) + ;; Generate float2 double ;; convert two double to float (define_expand "float2_v2df"