From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 14 Apr 2021 10:37:22 +0000 (+0100)
Subject: try chip_r adder test (works)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=648971d7841e7f223fdc6baa718022bbd1da6cd2;p=soc-cocotb-sim.git

try chip_r adder test (works)
---

diff --git a/ls180/post_pnr/cocotb/Makefile b/ls180/post_pnr/cocotb/Makefile
index cb4cc70..ea51d19 100644
--- a/ls180/post_pnr/cocotb/Makefile
+++ b/ls180/post_pnr/cocotb/Makefile
@@ -18,7 +18,7 @@ VHDL_SOURCES = \
   $(wildcard $(VSTDIR)/*.vst) \
   $(wildcard $(NSXLIBDIR)/*.vhd) \
   $(wildcard $(NIOLIBDIR)/*.vhd)
-TOPLEVEL=chip
+TOPLEVEL=chip_r
 TOPLEVEL_LANG=vhdl
 MODULE=test
 SIM=ghdl
diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index 4d79d0b..9bf57fd 100644
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -38,7 +38,7 @@ def setup_sim(dut, *, clk_period, run):
     dut.iovss <= 0
     dut.sys_rst <= 1
     dut.sys_clk <= 0
-    # adder test (ignore)
+    # adder test (ignore this)
     #dut.a <= 3
     #dut.b <= 2