From: Luke Kenneth Casson Leighton Date: Fri, 29 Mar 2019 11:33:28 +0000 (+0000) Subject: split out denorm to separate module X-Git-Tag: ls180-24jan2020~1405 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=648a09129b6d3c273264a3ea822ae86bea7f778b;p=ieee754fpu.git split out denorm to separate module --- diff --git a/src/add/fpcommon/denorm.py b/src/add/fpcommon/denorm.py new file mode 100644 index 00000000..32e77540 --- /dev/null +++ b/src/add/fpcommon/denorm.py @@ -0,0 +1,108 @@ +# IEEE Floating Point Adder (Single Precision) +# Copyright (C) Jonathan P Dawson 2013 +# 2013-12-12 + +from nmigen import Module, Signal, Cat, Mux, Array, Const +from nmigen.lib.coding import PriorityEncoder +from nmigen.cli import main, verilog +from math import log + +from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase +from fpbase import MultiShiftRMerge, Trigger +from singlepipe import (ControlBase, StageChain, UnbufferedPipeline, + PassThroughStage) +from multipipe import CombMuxOutPipe +from multipipe import PriorityCombMuxInPipe + +from fpbase import FPState +from fpcommon.getop import (FPGetOpMod, FPGetOp, FPNumBase2Ops, FPADDBaseData, FPGet2OpMod, FPGet2Op) + + +class FPSCData: + + def __init__(self, width, id_wid): + self.a = FPNumBase(width, True) + self.b = FPNumBase(width, True) + self.z = FPNumOut(width, False) + self.oz = Signal(width, reset_less=True) + self.out_do_z = Signal(reset_less=True) + self.mid = Signal(id_wid, reset_less=True) + + def eq(self, i): + return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), + self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)] + + +class FPAddDeNormMod(FPState): + + def __init__(self, width, id_wid): + self.width = width + self.id_wid = id_wid + self.i = self.ispec() + self.o = self.ospec() + + def ispec(self): + return FPSCData(self.width, self.id_wid) + + def ospec(self): + return FPSCData(self.width, self.id_wid) + + def process(self, i): + return self.o + + def setup(self, m, i): + """ links module to inputs and outputs + """ + m.submodules.denormalise = self + m.d.comb += self.i.eq(i) + + def elaborate(self, platform): + m = Module() + m.submodules.denorm_in_a = self.i.a + m.submodules.denorm_in_b = self.i.b + m.submodules.denorm_out_a = self.o.a + m.submodules.denorm_out_b = self.o.b + + with m.If(~self.i.out_do_z): + # XXX hmmm, don't like repeating identical code + m.d.comb += self.o.a.eq(self.i.a) + with m.If(self.i.a.exp_n127): + m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent + with m.Else(): + m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit + + m.d.comb += self.o.b.eq(self.i.b) + with m.If(self.i.b.exp_n127): + m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent + with m.Else(): + m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit + + m.d.comb += self.o.mid.eq(self.i.mid) + m.d.comb += self.o.z.eq(self.i.z) + m.d.comb += self.o.out_do_z.eq(self.i.out_do_z) + m.d.comb += self.o.oz.eq(self.i.oz) + + return m + + +class FPAddDeNorm(FPState): + + def __init__(self, width, id_wid): + FPState.__init__(self, "denormalise") + self.mod = FPAddDeNormMod(width) + self.out_a = FPNumBase(width) + self.out_b = FPNumBase(width) + + def setup(self, m, i): + """ links module to inputs and outputs + """ + self.mod.setup(m, i) + + m.d.sync += self.out_a.eq(self.mod.out_a) + m.d.sync += self.out_b.eq(self.mod.out_b) + + def action(self, m): + # Denormalised Number checks + m.next = "align" + + diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index cf375fe4..7be57bf2 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -16,21 +16,7 @@ from multipipe import PriorityCombMuxInPipe from fpbase import FPState from fpcommon.getop import (FPGetOpMod, FPGetOp, FPNumBase2Ops, FPADDBaseData, FPGet2OpMod, FPGet2Op) - - -class FPSCData: - - def __init__(self, width, id_wid): - self.a = FPNumBase(width, True) - self.b = FPNumBase(width, True) - self.z = FPNumOut(width, False) - self.oz = Signal(width, reset_less=True) - self.out_do_z = Signal(reset_less=True) - self.mid = Signal(id_wid, reset_less=True) - - def eq(self, i): - return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), - self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)] +from fpcommon.denorm import (FPSCData, FPAddDeNormMod, FPAddDeNorm) class FPAddSpecialCasesMod: @@ -240,79 +226,6 @@ class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline): m.next = "align" -class FPAddDeNormMod(FPState): - - def __init__(self, width, id_wid): - self.width = width - self.id_wid = id_wid - self.i = self.ispec() - self.o = self.ospec() - - def ispec(self): - return FPSCData(self.width, self.id_wid) - - def ospec(self): - return FPSCData(self.width, self.id_wid) - - def process(self, i): - return self.o - - def setup(self, m, i): - """ links module to inputs and outputs - """ - m.submodules.denormalise = self - m.d.comb += self.i.eq(i) - - def elaborate(self, platform): - m = Module() - m.submodules.denorm_in_a = self.i.a - m.submodules.denorm_in_b = self.i.b - m.submodules.denorm_out_a = self.o.a - m.submodules.denorm_out_b = self.o.b - - with m.If(~self.i.out_do_z): - # XXX hmmm, don't like repeating identical code - m.d.comb += self.o.a.eq(self.i.a) - with m.If(self.i.a.exp_n127): - m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent - with m.Else(): - m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit - - m.d.comb += self.o.b.eq(self.i.b) - with m.If(self.i.b.exp_n127): - m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent - with m.Else(): - m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit - - m.d.comb += self.o.mid.eq(self.i.mid) - m.d.comb += self.o.z.eq(self.i.z) - m.d.comb += self.o.out_do_z.eq(self.i.out_do_z) - m.d.comb += self.o.oz.eq(self.i.oz) - - return m - - -class FPAddDeNorm(FPState): - - def __init__(self, width, id_wid): - FPState.__init__(self, "denormalise") - self.mod = FPAddDeNormMod(width) - self.out_a = FPNumBase(width) - self.out_b = FPNumBase(width) - - def setup(self, m, i): - """ links module to inputs and outputs - """ - self.mod.setup(m, i) - - m.d.sync += self.out_a.eq(self.mod.out_a) - m.d.sync += self.out_b.eq(self.mod.out_b) - - def action(self, m): - # Denormalised Number checks - m.next = "align" - - class FPAddAlignMultiMod(FPState): def __init__(self, width):