From: lkcl <lkcl@web>
Date: Sun, 9 Oct 2022 21:35:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~120
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=649d9cda67b3c67128ed33f5626c3c71cfefd754;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index ed726432e..59e876ab3 100644
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -105,27 +105,27 @@ Book I as a new Section 4.6.2.1
 
 # Floating-Point Move Immediate
 
-`fmvis FRS, D`
+`fmvis FRT, D`
 
 |  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form    |
 |--------|------|-------|-------|-------|-----|---------|
-|  Major | FRS  | d1    | d0    | XO    | d2  | DX-Form |
+|  Major | FRT  | d1    | d0    | XO    | d2  | DX-Form |
 
 Pseudocode:
 
 ```
     bf16 <- d0 || d1 || d2 # create BF16 immediate
     fp32 <- bf16 || [0]*16 # convert BF16 to FP32
-    FRS <- DOUBLE(fp32)    # convert FP32 to FP64
+    FRT <- DOUBLE(fp32)    # convert FP32 to FP64
 ```
 
 Special registers altered:
 
     None
 
-Reinterprets `D << 16` as a 32-bit float, which is then converted to a
-64-bit float and written to `FRS`.  This is equivalent to reinterpreting
-`D` as a `BF16` and converting to 64-bit float.
+`D << 16` is interpreted as a 32-bit float, converted to a
+64-bit float and written to `FRT`.  This is equivalent to reinterpreting
+`D` as a `bfloat16` and converting to 64-bit float.
 
 Examples:
 
@@ -142,21 +142,21 @@ Examples:
 
 # Floating-Point Immediate Second-Half Move
 
-`fishmv FRS, D`
+`fishmv FRT, D`
 
 DX-Form:
 
 |  0-5   | 6-10 | 11-15 | 16-25 | 26-30 | 31  | Form    |
 |--------|------|-------|-------|-------|-----|---------|
-|  Major | FRS  | d1    | d0    | XO    | d2  | DX-Form |
+|  Major | FRT  | d1    | d0    | XO    | d2  | DX-Form |
 
 Pseudocode:
 
 ```
-    n <- (FRS)                     # read FRS
+    n <- (FRT)                     # read FRT
     fp32 <- SINGLE(n)              # convert to FP32
     fp32[16:31] <- d0 || d1 || d2  # replace LSB half
-    FRS <- DOUBLE(fp32)            # convert back to FP64
+    FRT <- DOUBLE(fp32)            # convert back to FP64
 ```
 
 Special registers altered:
@@ -164,12 +164,12 @@ Special registers altered:
     None
 
 An additional 16-bits of immediate is
-inserted into `FRS` to extend its accuracy to
+inserted into `FRT` to extend its accuracy to
 a full FP32, which is then stored in the usual FP64 Format within the FPR.
 
-**This instruction performs a Read-Modify-Write.** *FRS is read, the
+**This instruction performs a Read-Modify-Write.** *FRT is read, the
 additional
-16 bit immediate inserted, and the result also written to FRS.
+16 bit immediate inserted, and the result also written to FRT.
 This is strategically similar to how `li` combined with `oris` is
 used to construct 32-bit Integers.
 `fishmv` may be macro-op-fused with `fmvis`*