From: Palmer Dabbelt Date: Tue, 2 Oct 2018 15:26:32 +0000 (-0700) Subject: RISC-V: Add fence.tso instruction X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64a336ac134ebd7f9452a7088e90e29551465251;p=binutils-gdb.git RISC-V: Add fence.tso instruction The RISC-V memory model has been ratified, and it includes an additional fence: "fence.tso". This pseudo instruction extends one of the previously reserved full fence patterns to be less restrictive, and therefor will execute correctly on all existing microarchitectures. Thus there is no reason to allow this instruction to be disabled (or unconverted to a full fence), so it's just unconditionally allowed. I've added a test case for GAS to check that "fence.tso" correctly assembles on rv32i-based targets. I checked to see that "fence.tso" appears in "gas.log", but that's the only testing I've done. gas/ChangeLog 2018-10-02 Palmer Dabbelt * testsuite/gas/riscv/fence-tso.d: New file. * testsuite/gas/riscv/fence-tso.s: Likewise. include/ChangeLog 2018-10-02 Palmer Dabbelt * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define. (MASK_FENCE_TSO): Likewise. opcodes/ChangeLog 2018-10-02 Palmer Dabbelt * riscv-opc.c (riscv_opcodes) : New opcode. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 069f9cbf744..d6a4380efba 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2018-10-02 Palmer Dabbelt + + * testsuite/gas/riscv/fence-tso.d: New file. + * testsuite/gas/riscv/fence-tso.s: Likewise. + 2018-09-26 Sandra Loosemore * testsuite/gas/all/gas.exp: Skip "Output file must be distinct diff --git a/gas/testsuite/gas/riscv/fence-tso.d b/gas/testsuite/gas/riscv/fence-tso.d new file mode 100644 index 00000000000..ef8a4cdd1c9 --- /dev/null +++ b/gas/testsuite/gas/riscv/fence-tso.d @@ -0,0 +1,11 @@ +#as: -march=rv32ic +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+8330000f[ ]+fence.tso + diff --git a/gas/testsuite/gas/riscv/fence-tso.s b/gas/testsuite/gas/riscv/fence-tso.s new file mode 100644 index 00000000000..7770052b5e6 --- /dev/null +++ b/gas/testsuite/gas/riscv/fence-tso.s @@ -0,0 +1,2 @@ +target: + fence.tso diff --git a/include/ChangeLog b/include/ChangeLog index d0e0d7228d6..98d42416813 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2018-10-02 Palmer Dabbelt + + * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define. + (MASK_FENCE_TSO): Likewise. + 2018-10-01 Cupertino Miranda * arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 60bd2f999e8..f09200c073d 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -141,6 +141,8 @@ #define MASK_FENCE 0x707f #define MATCH_FENCE_I 0x100f #define MASK_FENCE_I 0x707f +#define MATCH_FENCE_TSO 0x8330000f +#define MASK_FENCE_TSO 0xfff0707f #define MATCH_MUL 0x2000033 #define MASK_MUL 0xfe00707f #define MATCH_MULH 0x2001033 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9b682850701..54baef056ca 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2018-10-02 Palmer Dabbelt + + * riscv-opc.c (riscv_opcodes) : New opcode. + 2018-09-23 Sandra Loosemore * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index e0f711811f6..b6843f24373 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -342,6 +342,7 @@ const struct riscv_opcode riscv_opcodes[] = {"fence", 0, {"I", 0}, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, {"fence", 0, {"I", 0}, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, {"fence.i", 0, {"I", 0}, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, +{"fence.tso", 0, {"I", 0}, "", MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS }, {"rdcycle", 0, {"I", 0}, "d", MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS }, {"rdinstret", 0, {"I", 0}, "d", MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS }, {"rdtime", 0, {"I", 0}, "d", MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },