From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 21:50:11 +0000 (-0700)
Subject: Do not perform width-checks for DSP48E1 which is much more complicated
X-Git-Tag: working-ls180~1039^2~87
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64a72ed51e9d21cf5f30e3ff87856c808cf53a29;p=yosys.git

Do not perform width-checks for DSP48E1 which is much more complicated
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index c6120695a..f0537670f 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -278,17 +278,6 @@ endmatch
 code sigC sigP
 	if (postAdd) {
 		sigC = port(postAdd, postAddAB == \A ? \B : \A);
-
-		// TODO for DSP48E1, which will have sign extended inputs/outputs
-		//int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
-		//int actual_mul_width = GetSize(sigP);
-		//int actual_acc_width = GetSize(sigC);
-
-		//if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
-		//	reject;
-		//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(postAdd, \A_SIGNED).as_bool()))
-		//	reject;
-
 		sigP = port(postAdd, \Y);
 	}
 endcode