From: Luke Kenneth Casson Leighton Date: Mon, 2 Mar 2020 20:28:47 +0000 (+0000) Subject: add fpmul64.il test, to see how long it takes (10 minutes, 6000x6000) X-Git-Tag: partial-core-ls180-gdsii~183 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64a8ef8df712abbffc175d212e603f7a79c6212c;p=soclayout.git add fpmul64.il test, to see how long it takes (10 minutes, 6000x6000) --- diff --git a/experiments6/Makefile b/experiments6/Makefile new file mode 100755 index 0000000..8ac69c5 --- /dev/null +++ b/experiments6/Makefile @@ -0,0 +1,27 @@ +# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*- + + LOGICAL_SYNTHESIS = Yosys + PHYSICAL_SYNTHESIS = Coriolis + DESIGN_KIT = sxlib + + YOSYS_FLATTEN = Yes + CORE = fpmul64 + USE_CLOCKTREE = Yes + USE_DEBUG = No + USE_KITE = No + + NETLISTS = $(shell cat nets2.txt) + + VST_FLAGS = --vst-use-concat + + include ./mk/design-flow.mk + + +blif: fpmul64.blif +vst: fpmul64.vst +layout: fpmul64_cts_r.ap +gds: fpmul64_cts_r.gds + +lvx: lvx-fpmul64_cts_r +druc: druc-fpmul64_cts_r +view: cgt-fpmul64_cts_r diff --git a/experiments6/coriolis2/__init__.py b/experiments6/coriolis2/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/experiments6/coriolis2/katana.py b/experiments6/coriolis2/katana.py new file mode 100644 index 0000000..442b2fc --- /dev/null +++ b/experiments6/coriolis2/katana.py @@ -0,0 +1,12 @@ + +from Hurricane import DebugSession + +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) ) diff --git a/experiments6/coriolis2/settings.py b/experiments6/coriolis2/settings.py new file mode 100644 index 0000000..95cc039 --- /dev/null +++ b/experiments6/coriolis2/settings.py @@ -0,0 +1,56 @@ +# -*- Mode:Python -*- + +import os +import Cfg +import CRL +import Viewer +#import node180.scn6m_deep_09 +import symbolic.cmos +from helpers import l, u, n + + +Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile ) + + +Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + +Cfg.getParamBool ( 'misc.catchCore' ).setBool ( False ) +Cfg.getParamBool ( 'misc.info' ).setBool ( False ) +Cfg.getParamBool ( 'misc.paranoid' ).setBool ( False ) +Cfg.getParamBool ( 'misc.bug' ).setBool ( False ) +Cfg.getParamBool ( 'misc.logMode' ).setBool ( True ) +Cfg.getParamBool ( 'misc.verboseLevel1' ).setBool ( True ) +Cfg.getParamBool ( 'misc.verboseLevel2' ).setBool ( True ) +Cfg.getParamInt ( 'misc.minTraceLevel' ).setInt ( 159 ) +Cfg.getParamInt ( 'misc.maxTraceLevel' ).setInt ( 160 ) +Cfg.getParamEnumerate ( 'etesian.effort' ).setInt ( 2 ) +Cfg.getParamPercentage( 'etesian.spaceMargin' ).setPercentage( 20.0 ) +Cfg.getParamPercentage( 'etesian.aspectRatio' ).setPercentage( 100.0 ) +Cfg.getParamBool ( 'etesian.uniformDensity' ).setBool ( True ) +Cfg.getParamInt ( 'anabatic.edgeLenght' ).setInt ( 24 ) +Cfg.getParamInt ( 'anabatic.edgeWidth' ).setInt ( 8 ) +Cfg.getParamString ( 'anabatic.topRoutingLayer' ).setString ( 'METAL5') +Cfg.getParamInt ( 'katana.eventsLimit' ).setInt ( 1000000 ) +Cfg.getParamInt ( 'katana.hTracksReservedLocal' ).setInt ( 7 ) +Cfg.getParamInt ( 'katana.vTracksReservedLocal' ).setInt ( 6 ) +#Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(1000) ) + +Cfg.Configuration.popDefaultPriority() + +#cellsTop = os.path.abspath( os.getcwd()+'/../cells' ) +if os.environ.has_key('CELLS_TOP'): + cellsTop = os.environ['CELLS_TOP'] +else: + cellsTop = '../../../cells' + +af = CRL.AllianceFramework.get() +env = af.getEnvironment() +env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend ) +env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend ) +env.setCLOCK( '^clk$|m_clock' ) +env.setPOWER( 'vdd' ) +env.setGROUND( 'vss' ) + + +print 'Successfully read user configuration' + diff --git a/experiments6/fpmul64.il b/experiments6/fpmul64.il new file mode 100644 index 0000000..c01c6e0 --- /dev/null +++ b/experiments6/fpmul64.il @@ -0,0 +1,11605 @@ +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.inpipe.p0" +module \p0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 0 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 1 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.inpipe.p1" +module \p1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 0 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 1 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.inpipe.p2" +module \p2 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 0 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 1 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.inpipe.p3" +module \p3 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 0 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 1 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.inpipe.n" +module \n + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.inpipe.p_mux.selector" +module \selector + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75" + wire width 4 input 0 \i + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77" + wire width 1 output 1 \n + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 2 output 2 \o + process $group_0 + assign \o 2'00 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 2'11 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 2'10 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 2'01 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 2'00 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.inpipe.p_mux" +module \p_mux + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:542" + wire width 2 output 0 \m_id + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:543" + wire width 1 output 1 \active + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 2 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 3 \p_valid_i__1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 4 \p_valid_i__2 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 5 \p_valid_i__3 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75" + wire width 4 \selector_i + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77" + wire width 1 \selector_n + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 2 \selector_o + cell \selector \selector + connect \i \selector_i + connect \n \selector_n + connect \o \selector_o + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:556" + wire width 1 \p_valid_i__4 + process $group_0 + assign \p_valid_i__4 1'0 + assign \p_valid_i__4 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:556" + wire width 1 \p_valid_i__5 + process $group_1 + assign \p_valid_i__5 1'0 + assign \p_valid_i__5 \p_valid_i__1 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:556" + wire width 1 \p_valid_i__6 + process $group_2 + assign \p_valid_i__6 1'0 + assign \p_valid_i__6 \p_valid_i__2 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:556" + wire width 1 \p_valid_i__7 + process $group_3 + assign \p_valid_i__7 1'0 + assign \p_valid_i__7 \p_valid_i__3 + sync init + end + process $group_4 + assign \selector_i 4'0000 + assign \selector_i { \p_valid_i__7 \p_valid_i__6 \p_valid_i__5 \p_valid_i__4 } + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:566" + wire width 1 $8 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:566" + cell $not $9 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \selector_n + connect \Y $8 + end + process $group_5 + assign \active 1'0 + assign \active $8 + sync init + end + process $group_6 + assign \m_id 2'00 + assign \m_id \selector_o + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.inpipe" +module \inpipe + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 output 2 \a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 output 3 \b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 output 4 \c + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 5 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 6 \op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 7 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 8 \p_ready_o__1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 9 \p_ready_o__2 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 10 \p_ready_o__3 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 11 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 12 \a__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 13 \b__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 14 \c__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 15 \muxid__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 16 \op__8 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 17 \p_valid_i__9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 18 \a__10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 19 \b__11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 20 \c__12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 21 \muxid__13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 22 \op__14 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 23 \p_valid_i__15 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 24 \a__16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 25 \b__17 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 26 \c__18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 27 \muxid__19 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 28 \op__20 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 29 \p_valid_i__21 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 30 \a__22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 31 \b__23 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 32 \c__24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 33 \muxid__25 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 34 \op__26 + cell \p0 \p0 + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + cell \p1 \p1 + connect \p_ready_o \p_ready_o__1 + connect \p_valid_i \p_valid_i__9 + end + cell \p2 \p2 + connect \p_ready_o \p_ready_o__2 + connect \p_valid_i \p_valid_i__15 + end + cell \p3 \p3 + connect \p_ready_o \p_ready_o__3 + connect \p_valid_i \p_valid_i__21 + end + cell \n \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:542" + wire width 2 \p_mux_m_id + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:543" + wire width 1 \p_mux_active + cell \p_mux \p_mux + connect \m_id \p_mux_m_id + connect \active \p_mux_active + connect \p_valid_i \p_valid_i + connect \p_valid_i__1 \p_valid_i__9 + connect \p_valid_i__2 \p_valid_i__15 + connect \p_valid_i__3 \p_valid_i__21 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:315" + wire width 1 \nirn + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:316" + wire width 1 $27 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:316" + cell $not $28 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \Y $27 + end + process $group_0 + assign \nirn 1'0 + assign \nirn $27 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:303" + wire width 1 \data_valid + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:303" + wire width 1 \data_valid__29 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:303" + wire width 1 \data_valid__30 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:303" + wire width 1 \data_valid__31 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:304" + wire width 1 \p_valid_i__32 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:305" + wire width 1 \n_ready_in + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341" + wire width 1 $33 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341" + cell $or $34 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__32 + connect \B \n_ready_in + connect \Y $33 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:304" + wire width 1 \p_valid_i__35 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:305" + wire width 1 \n_ready_in__36 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341" + wire width 1 $37 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341" + cell $or $38 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__35 + connect \B \n_ready_in__36 + connect \Y $37 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:304" + wire width 1 \p_valid_i__39 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:305" + wire width 1 \n_ready_in__40 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341" + wire width 1 $41 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341" + cell $or $42 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__39 + connect \B \n_ready_in__40 + connect \Y $41 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:304" + wire width 1 \p_valid_i__43 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:305" + wire width 1 \n_ready_in__44 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341" + wire width 1 $45 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:341" + cell $or $46 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__43 + connect \B \n_ready_in__44 + connect \Y $45 + end + process $group_1 + assign \data_valid 1'0 + assign \data_valid__29 1'0 + assign \data_valid__30 1'0 + assign \data_valid__31 1'0 + assign \data_valid 1'0 + assign \data_valid__29 1'0 + assign \data_valid__30 1'0 + assign \data_valid__31 1'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:340" + switch \p_mux_m_id + case 2'00 + assign \data_valid $33 + case 2'01 + assign \data_valid__29 $37 + case 2'10 + assign \data_valid__30 $41 + case 2'-- + assign \data_valid__31 $45 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + wire width 1 $47 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + cell $and $48 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \nirn + connect \B \data_valid + connect \Y $47 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + wire width 1 $49 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + cell $and $50 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \nirn + connect \B \data_valid__29 + connect \Y $49 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + wire width 1 $51 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + cell $and $52 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \nirn + connect \B \data_valid__30 + connect \Y $51 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + wire width 1 $53 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + cell $and $54 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \nirn + connect \B \data_valid__31 + connect \Y $53 + end + process $group_2 + assign \n_ready_in 1'0 + assign \n_ready_in__36 1'0 + assign \n_ready_in__40 1'0 + assign \n_ready_in__44 1'0 + assign \n_ready_in 1'1 + assign \n_ready_in__36 1'1 + assign \n_ready_in__40 1'1 + assign \n_ready_in__44 1'1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:333" + switch \p_mux_m_id + case 2'00 + assign \n_ready_in $47 + case 2'01 + assign \n_ready_in__36 $49 + case 2'10 + assign \n_ready_in__40 $51 + case 2'-- + assign \n_ready_in__44 $53 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:326" + wire width 1 \maskedout + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + wire width 1 $55 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + cell $and $56 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout + connect \B \p_mux_active + connect \Y $55 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + wire width 1 $57 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + cell $and $58 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout + connect \B \p_mux_active + connect \Y $57 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + wire width 1 $59 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + cell $and $60 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout + connect \B \p_mux_active + connect \Y $59 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + wire width 1 $61 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + cell $and $62 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout + connect \B \p_mux_active + connect \Y $61 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + wire width 1 $63 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + cell $and $64 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout + connect \B \p_mux_active + connect \Y $63 + end + process $group_3 + assign \p_valid_i__32 1'0 + assign \p_valid_i__35 1'0 + assign \p_valid_i__39 1'0 + assign \p_valid_i__43 1'0 + assign \p_valid_i__32 1'0 + assign \p_valid_i__35 1'0 + assign \p_valid_i__39 1'0 + assign \p_valid_i__43 1'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:331" + switch \p_mux_m_id + case 2'00 + assign \p_valid_i__32 $57 + case 2'01 + assign \p_valid_i__35 $59 + case 2'10 + assign \p_valid_i__39 $61 + case 2'-- + assign \p_valid_i__43 $63 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $65 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $66 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + cell $not $67 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \data_valid + connect \Y $66 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $68 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + cell $or $69 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $66 + connect \B \n_ready_i + connect \Y $68 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $70 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + cell $not $71 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \data_valid__29 + connect \Y $70 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $72 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + cell $or $73 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $70 + connect \B \n_ready_i + connect \Y $72 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $74 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + cell $not $75 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \data_valid__30 + connect \Y $74 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $76 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + cell $or $77 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $74 + connect \B \n_ready_i + connect \Y $76 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $78 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + cell $not $79 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \data_valid__31 + connect \Y $78 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + wire width 1 $80 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + cell $or $81 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $78 + connect \B \n_ready_i + connect \Y $80 + end + process $group_4 + assign \p_ready_o 1'0 + assign \p_ready_o__1 1'0 + assign \p_ready_o__2 1'0 + assign \p_ready_o__3 1'0 + assign \p_ready_o 1'0 + assign \p_ready_o__1 1'0 + assign \p_ready_o__2 1'0 + assign \p_ready_o__3 1'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:332" + switch \p_mux_m_id + case 2'00 + assign \p_ready_o $68 + case 2'01 + assign \p_ready_o__1 $72 + case 2'10 + assign \p_ready_o__2 $76 + case 2'-- + assign \p_ready_o__3 $80 + end + sync init + end + wire width 1 $verilog_initial_trigger + process $group_17 + assign \maskedout 1'0 + assign \maskedout 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:339" + wire width 1 $82 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:339" + cell $reduce_bool $83 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 1'1 + connect \A { \data_valid__31 \data_valid__30 \data_valid__29 \data_valid } + connect \Y $82 + end + process $group_18 + assign \n_valid_o 1'0 + assign \n_valid_o $82 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:366" + wire width 1 \maskedout__84 + process $group_19 + assign \maskedout__84 1'0 + assign \maskedout__84 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:365" + wire width 1 \vr + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $85 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $reduce_bool $86 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout__84 + connect \Y $85 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $87 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $and $88 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $85 + connect \B \p_valid_i + connect \Y $87 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $89 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $and $90 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $87 + connect \B \p_ready_o + connect \Y $89 + end + process $group_20 + assign \vr 1'0 + assign \vr $89 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \a__91 + process $group_21 + assign \a__91 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \a__91 \a__4 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \b__92 + process $group_22 + assign \b__92 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \b__92 \b__5 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \c__93 + process $group_23 + assign \c__93 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \c__93 \c__6 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__94 + process $group_24 + assign \muxid__94 2'00 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \muxid__94 \muxid__7 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__95 + process $group_25 + assign \op__95 0'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \op__95 \op__8 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:366" + wire width 1 \maskedout__96 + process $group_26 + assign \maskedout__96 1'0 + assign \maskedout__96 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:365" + wire width 1 \vr__97 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $98 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $reduce_bool $99 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout__96 + connect \Y $98 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $100 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $and $101 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $98 + connect \B \p_valid_i__9 + connect \Y $100 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $102 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $and $103 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $100 + connect \B \p_ready_o__1 + connect \Y $102 + end + process $group_27 + assign \vr__97 1'0 + assign \vr__97 $102 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \a__104 + process $group_28 + assign \a__104 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__97 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \a__104 \a__10 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \b__105 + process $group_29 + assign \b__105 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__97 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \b__105 \b__11 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \c__106 + process $group_30 + assign \c__106 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__97 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \c__106 \c__12 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__107 + process $group_31 + assign \muxid__107 2'00 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__97 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \muxid__107 \muxid__13 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__108 + process $group_32 + assign \op__108 0'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__97 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \op__108 \op__14 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:366" + wire width 1 \maskedout__109 + process $group_33 + assign \maskedout__109 1'0 + assign \maskedout__109 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:365" + wire width 1 \vr__110 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $111 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $reduce_bool $112 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout__109 + connect \Y $111 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $113 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $and $114 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $111 + connect \B \p_valid_i__15 + connect \Y $113 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $115 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $and $116 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $113 + connect \B \p_ready_o__2 + connect \Y $115 + end + process $group_34 + assign \vr__110 1'0 + assign \vr__110 $115 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \a__117 + process $group_35 + assign \a__117 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__110 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \a__117 \a__16 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \b__118 + process $group_36 + assign \b__118 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__110 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \b__118 \b__17 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \c__119 + process $group_37 + assign \c__119 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__110 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \c__119 \c__18 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__120 + process $group_38 + assign \muxid__120 2'00 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__110 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \muxid__120 \muxid__19 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__121 + process $group_39 + assign \op__121 0'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__110 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \op__121 \op__20 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:366" + wire width 1 \maskedout__122 + process $group_40 + assign \maskedout__122 1'0 + assign \maskedout__122 1'1 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:365" + wire width 1 \vr__123 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $124 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $reduce_bool $125 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \maskedout__122 + connect \Y $124 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $126 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $and $127 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $124 + connect \B \p_valid_i__21 + connect \Y $126 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + wire width 1 $128 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:371" + cell $and $129 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $126 + connect \B \p_ready_o__3 + connect \Y $128 + end + process $group_41 + assign \vr__123 1'0 + assign \vr__123 $128 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \a__130 + process $group_42 + assign \a__130 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__123 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \a__130 \a__22 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \b__131 + process $group_43 + assign \b__131 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__123 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \b__131 \b__23 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \c__132 + process $group_44 + assign \c__132 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__123 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \c__132 \c__24 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__133 + process $group_45 + assign \muxid__133 2'00 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__123 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \muxid__133 \muxid__25 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__134 + process $group_46 + assign \op__134 0'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + switch { \vr__123 } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:372" + case 1'1 + assign \op__134 \op__26 + end + sync init + end + process $group_47 + assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:25" + switch \p_mux_m_id + case 2'00 + assign \a \a__91 + case 2'01 + assign \a \a__104 + case 2'10 + assign \a \a__117 + case 2'-- + assign \a \a__130 + end + sync init + end + process $group_48 + assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:25" + switch \p_mux_m_id + case 2'00 + assign \b \b__92 + case 2'01 + assign \b \b__105 + case 2'10 + assign \b \b__118 + case 2'-- + assign \b \b__131 + end + sync init + end + process $group_49 + assign \c 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:25" + switch \p_mux_m_id + case 2'00 + assign \c \c__93 + case 2'01 + assign \c \c__106 + case 2'10 + assign \c \c__119 + case 2'-- + assign \c \c__132 + end + sync init + end + process $group_50 + assign \muxid 2'00 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:68" + switch \p_mux_m_id + case 2'00 + assign \muxid \muxid__94 + case 2'01 + assign \muxid \muxid__107 + case 2'10 + assign \muxid \muxid__120 + case 2'-- + assign \muxid \muxid__133 + end + sync init + end + process $group_51 + assign \op 0'0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:69" + switch \p_mux_m_id + case 2'00 + assign \op \op__95 + case 2'01 + assign \op \op__108 + case 2'10 + assign \op \op__121 + case 2'-- + assign \op \op__134 + end + sync init + end + connect \op 0'0 + connect \op__95 0'0 + connect \op__108 0'0 + connect \op__121 0'0 + connect \op__134 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.p" +module \p + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.n" +module \n__1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.p" +module \p__2 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.n" +module \n__3 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.specialcases.sc_decode_a" +module \sc_decode_a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366" + wire width 64 input 0 \v + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 1 \s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 2 \e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 3 \m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 output 4 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 output 5 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 output 6 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:697" + wire width 53 $32 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:697" + cell $pos $33 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110100 + parameter \Y_WIDTH 6'110101 + connect \A { \v [51:0] } + connect \Y $32 + end + process $group_15 + assign \m 53'00000000000000000000000000000000000000000000000000000 + assign \m $32 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698" + wire width 14 $34 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223" + wire width 13 $35 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223" + cell $pos $36 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 4'1011 + parameter \Y_WIDTH 4'1101 + connect \A \v [62:52] + connect \Y $35 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698" + wire width 14 $37 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698" + cell $sub $38 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A $35 + connect \B 13'0001111111111 + connect \Y $37 + end + connect $34 $37 + process $group_16 + assign \e 13'0000000000000 + assign \e $34 [12:0] + sync init + end + process $group_17 + assign \s 1'0 + assign \s \v [63] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.specialcases.sc_decode_b" +module \sc_decode_b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366" + wire width 64 input 0 \v + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 1 \s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 2 \e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 3 \m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 output 4 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 output 5 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 output 6 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:697" + wire width 53 $32 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:697" + cell $pos $33 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110100 + parameter \Y_WIDTH 6'110101 + connect \A { \v [51:0] } + connect \Y $32 + end + process $group_15 + assign \m 53'00000000000000000000000000000000000000000000000000000 + assign \m $32 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698" + wire width 14 $34 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223" + wire width 13 $35 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223" + cell $pos $36 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 4'1011 + parameter \Y_WIDTH 4'1101 + connect \A \v [62:52] + connect \Y $35 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698" + wire width 14 $37 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:698" + cell $sub $38 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A $35 + connect \B 13'0001111111111 + connect \Y $37 + end + connect $34 $37 + process $group_16 + assign \e 13'0000000000000 + assign \e $34 [12:0] + sync init + end + process $group_17 + assign \s 1'0 + assign \s \v [63] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.specialcases" +module \specialcases + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 0 \a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 1 \b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 2 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 3 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 output 4 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 output 5 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 6 \a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 7 \a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 8 \a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 9 \b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 10 \b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 11 \b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 12 \muxid__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 13 \op__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366" + wire width 64 \sc_decode_a_v + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \sc_decode_a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \sc_decode_a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \sc_decode_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \sc_decode_a_is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \sc_decode_a_is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \sc_decode_a_is_nan + cell \sc_decode_a \sc_decode_a + connect \v \sc_decode_a_v + connect \s \sc_decode_a_s + connect \e \sc_decode_a_e + connect \m \sc_decode_a_m + connect \is_zero \sc_decode_a_is_zero + connect \is_inf \sc_decode_a_is_inf + connect \is_nan \sc_decode_a_is_nan + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366" + wire width 64 \sc_decode_b_v + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \sc_decode_b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \sc_decode_b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \sc_decode_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \sc_decode_b_is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \sc_decode_b_is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \sc_decode_b_is_nan + cell \sc_decode_b \sc_decode_b + connect \v \sc_decode_b_v + connect \s \sc_decode_b_s + connect \e \sc_decode_b_e + connect \m \sc_decode_b_m + connect \is_zero \sc_decode_b_is_zero + connect \is_inf \sc_decode_b_is_inf + connect \is_nan \sc_decode_b_is_nan + end + process $group_0 + assign \sc_decode_a_v 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sc_decode_a_v \a + sync init + end + process $group_1 + assign \sc_decode_b_v 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \sc_decode_b_v \b + sync init + end + process $group_2 + assign \a_s 1'0 + assign \a_s \sc_decode_a_s + sync init + end + process $group_3 + assign \a_e 13'0000000000000 + assign \a_e \sc_decode_a_e + sync init + end + process $group_4 + assign \a_m 53'00000000000000000000000000000000000000000000000000000 + assign \a_m \sc_decode_a_m + sync init + end + process $group_5 + assign \b_s 1'0 + assign \b_s \sc_decode_b_s + sync init + end + process $group_6 + assign \b_e 13'0000000000000 + assign \b_e \sc_decode_b_e + sync init + end + process $group_7 + assign \b_m 53'00000000000000000000000000000000000000000000000000000 + assign \b_m \sc_decode_b_m + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:57" + wire width 1 \sabx + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:59" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:59" + cell $xor $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \sc_decode_a_s + connect \B \sc_decode_b_s + connect \Y $3 + end + process $group_8 + assign \sabx 1'0 + assign \sabx $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:52" + wire width 1 \t_obz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:60" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:60" + cell $or $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \sc_decode_a_is_zero + connect \B \sc_decode_b_is_zero + connect \Y $5 + end + process $group_9 + assign \t_obz 1'0 + assign \t_obz $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:53" + wire width 1 \t_a1inf + process $group_10 + assign \t_a1inf 1'0 + assign \t_a1inf \sc_decode_a_is_inf + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:54" + wire width 1 \t_b1inf + process $group_11 + assign \t_b1inf 1'0 + assign \t_b1inf \sc_decode_b_is_inf + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:55" + wire width 1 \t_abnan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:63" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:63" + cell $or $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \sc_decode_a_is_nan + connect \B \sc_decode_b_is_nan + connect \Y $7 + end + process $group_12 + assign \t_abnan 1'0 + assign \t_abnan $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:56" + wire width 1 \t_special + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:64" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:64" + cell $reduce_bool $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 1'1 + connect \A { \t_a1inf \t_b1inf \t_abnan \t_obz } + connect \Y $9 + end + process $group_13 + assign \t_special 1'0 + assign \t_special $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366" + wire width 64 \z_zero_v + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + cell $add $13 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A 13'1110000000001 + connect \B 13'0001111111111 + connect \Y $12 + end + connect $11 $12 + process $group_14 + assign \z_zero_v 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z_zero_v [51:0] 52'0000000000000000000000000000000000000000000000000000 + assign \z_zero_v [62:52] $11 [10:0] + assign \z_zero_v [63] \sabx + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366" + wire width 64 \z_nan_v + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $15 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + cell $add $16 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A 13'0010000000000 + connect \B 13'0001111111111 + connect \Y $15 + end + connect $14 $15 + wire width 1 $verilog_initial_trigger + process $group_15 + assign \z_nan_v 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z_nan_v [51:0] 52'1000000000000000000000000000000000000000000000000000 + assign \z_nan_v [62:52] $14 [10:0] + assign \z_nan_v [63] 1'0 + assign $verilog_initial_trigger $verilog_initial_trigger + sync init + update $verilog_initial_trigger 1'0 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366" + wire width 64 \z_inf_v + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $17 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + cell $add $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A 13'0010000000000 + connect \B 13'0001111111111 + connect \Y $18 + end + connect $17 $18 + process $group_16 + assign \z_inf_v 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z_inf_v [51:0] 52'0000000000000000000000000000000000000000000000000000 + assign \z_inf_v [62:52] $17 [10:0] + assign \z_inf_v [63] \sabx + sync init + end + process $group_17 + assign \out_do_z 1'0 + assign \out_do_z \t_special + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:89" + wire width 64 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:89" + cell $mux $21 + parameter \WIDTH 7'1000000 + connect \A \z_inf_v + connect \B \z_nan_v + connect \S \sc_decode_b_is_zero + connect \Y $20 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:88" + wire width 64 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:88" + cell $mux $23 + parameter \WIDTH 7'1000000 + connect \A \z_inf_v + connect \B \z_nan_v + connect \S \sc_decode_a_is_zero + connect \Y $22 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:87" + wire width 64 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:87" + cell $mux $25 + parameter \WIDTH 7'1000000 + connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \B \z_zero_v + connect \S \t_obz + connect \Y $24 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:88" + wire width 64 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:88" + cell $mux $27 + parameter \WIDTH 7'1000000 + connect \A $24 + connect \B $22 + connect \S \t_b1inf + connect \Y $26 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:89" + wire width 64 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:89" + cell $mux $29 + parameter \WIDTH 7'1000000 + connect \A $26 + connect \B $20 + connect \S \t_a1inf + connect \Y $28 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:90" + wire width 64 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/specialcases.py:90" + cell $mux $31 + parameter \WIDTH 7'1000000 + connect \A $28 + connect \B \z_nan_v + connect \S \t_abnan + connect \Y $30 + end + process $group_18 + assign \oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz $30 + sync init + end + process $group_19 + assign \muxid__1 2'00 + assign \muxid__1 \muxid + sync init + end + process $group_20 + assign \op__2 0'0 + assign \op__2 \op + sync init + end + connect \op__2 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.denormalise.denorm_in_a" +module \denorm_in_a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 0 \a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 1 \a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 output 2 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \a_e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \a_m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \a_m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.denormalise.denorm_in_b" +module \denorm_in_b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 0 \b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 1 \b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 output 2 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \b_e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \b_m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \b_m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.denormalise" +module \denormalise + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 0 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 1 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 2 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 input 3 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 input 4 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 5 \a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 6 \a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 7 \a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 8 \b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 9 \b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 10 \b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 11 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 12 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 13 \z_s__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 14 \z_e__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 15 \z_m__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 output 16 \out_do_z__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 output 17 \oz__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 18 \a_s__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 19 \a_e__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 20 \a_m__8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 21 \b_s__9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 22 \b_e__10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 23 \b_m__11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 24 \muxid__12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 25 \op__13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \denorm_in_a_exp_n127 + cell \denorm_in_a \denorm_in_a + connect \a_e \a_e + connect \a_m \a_m + connect \exp_n127 \denorm_in_a_exp_n127 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \denorm_in_b_exp_n127 + cell \denorm_in_b \denorm_in_b + connect \b_e \b_e + connect \b_m \b_m + connect \exp_n127 \denorm_in_b_exp_n127 + end + process $group_0 + assign \a_s__6 1'0 + assign \a_s__6 \a_s + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:40" + wire width 13 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:40" + cell $mux $15 + parameter \WIDTH 4'1101 + connect \A \a_e + connect \B 13'1110000000010 + connect \S \denorm_in_a_exp_n127 + connect \Y $14 + end + process $group_1 + assign \a_e__7 13'0000000000000 + assign \a_e__7 \a_e + assign \a_e__7 $14 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:41" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:41" + cell $mux $17 + parameter \WIDTH 1'1 + connect \A 1'1 + connect \B \a_m [52] + connect \S \denorm_in_a_exp_n127 + connect \Y $16 + end + process $group_2 + assign \a_m__8 53'00000000000000000000000000000000000000000000000000000 + assign \a_m__8 \a_m + assign \a_m__8 [52] $16 + sync init + end + process $group_3 + assign \b_s__9 1'0 + assign \b_s__9 \b_s + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:48" + wire width 13 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:48" + cell $mux $19 + parameter \WIDTH 4'1101 + connect \A \b_e + connect \B 13'1110000000010 + connect \S \denorm_in_b_exp_n127 + connect \Y $18 + end + process $group_4 + assign \b_e__10 13'0000000000000 + assign \b_e__10 \b_e + assign \b_e__10 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:49" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/denorm.py:49" + cell $mux $21 + parameter \WIDTH 1'1 + connect \A 1'1 + connect \B \b_m [52] + connect \S \denorm_in_b_exp_n127 + connect \Y $20 + end + process $group_5 + assign \b_m__11 53'00000000000000000000000000000000000000000000000000000 + assign \b_m__11 \b_m + assign \b_m__11 [52] $20 + sync init + end + process $group_6 + assign \muxid__12 2'00 + assign \muxid__12 \muxid + sync init + end + process $group_7 + assign \op__13 0'0 + assign \op__13 \op + sync init + end + process $group_8 + assign \z_s__1 1'0 + assign \z_s__1 \z_s + sync init + end + process $group_9 + assign \z_e__2 13'0000000000000 + assign \z_e__2 \z_e + sync init + end + process $group_10 + assign \z_m__3 53'00000000000000000000000000000000000000000000000000000 + assign \z_m__3 \z_m + sync init + end + process $group_11 + assign \out_do_z__4 1'0 + assign \out_do_z__4 \out_do_z + sync init + end + process $group_12 + assign \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__5 \oz + sync init + end + connect \op__13 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.align.norm1_insel_a" +module \norm1_insel_a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 0 \a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 1 \i_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 output 2 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \a_e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \a_e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \i_a_m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \i_a_m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.align.norm1_insel_b" +module \norm1_insel_b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 0 \b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 1 \i_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 output 2 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \b_e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \b_e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \i_b_m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \i_b_m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.align.norm_pe_a.pe" +module \pe + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75" + wire width 53 input 0 \i + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 6 output 1 \o + process $group_0 + assign \o 6'000000 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [52] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [51] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [50] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [49] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [48] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [47] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [46] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [45] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [44] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [43] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [42] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [41] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [40] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [39] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [38] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [37] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [36] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [35] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [34] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [33] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [32] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [31] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [30] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [29] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [28] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [27] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [26] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [25] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [24] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [23] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [22] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [21] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [20] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [19] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [18] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [17] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [16] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [15] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [14] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [13] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [12] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [11] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [10] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [9] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [8] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000000 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77" + wire width 1 \n + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.align.norm_pe_a" +module \norm_pe_a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31" + wire width 53 input 0 \m_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32" + wire width 13 input 1 \e_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34" + wire width 13 output 2 \e_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33" + wire width 53 output 3 \m_out + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75" + wire width 53 \pe_i + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 6 \pe_o + cell \pe \pe + connect \i \pe_i + connect \o \pe_o + end + process $group_0 + assign \pe_i 53'00000000000000000000000000000000000000000000000000000 + assign \pe_i { \m_in [0] \m_in [1] \m_in [2] \m_in [3] \m_in [4] \m_in [5] \m_in [6] \m_in [7] \m_in [8] \m_in [9] \m_in [10] \m_in [11] \m_in [12] \m_in [13] \m_in [14] \m_in [15] \m_in [16] \m_in [17] \m_in [18] \m_in [19] \m_in [20] \m_in [21] \m_in [22] \m_in [23] \m_in [24] \m_in [25] \m_in [26] \m_in [27] \m_in [28] \m_in [29] \m_in [30] \m_in [31] \m_in [32] \m_in [33] \m_in [34] \m_in [35] \m_in [36] \m_in [37] \m_in [38] \m_in [39] \m_in [40] \m_in [41] \m_in [42] \m_in [43] \m_in [44] \m_in [45] \m_in [46] \m_in [47] \m_in [48] \m_in [49] \m_in [50] \m_in [51] \m_in [52] } + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:48" + wire width 13 \clz + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 13 $1 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + cell $pos $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'110 + parameter \Y_WIDTH 4'1101 + connect \A \pe_o + connect \Y $1 + end + process $group_1 + assign \clz 13'0000000000000 + assign \clz $1 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:50" + wire width 13 \uclz + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 13 $3 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + cell $pos $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'110 + parameter \Y_WIDTH 4'1101 + connect \A \pe_o + connect \Y $3 + end + process $group_2 + assign \uclz 13'0000000000000 + assign \uclz $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:51" + wire width 53 \temp + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + wire width 8244 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + wire width 8244 $6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + cell $sshl $7 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 14'10000000110100 + connect \A \m_in + connect \B \uclz + connect \Y $6 + end + connect $5 $6 + process $group_3 + assign \temp 53'00000000000000000000000000000000000000000000000000000 + assign \temp $5 [52:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + wire width 14 $8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + wire width 14 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + cell $sub $10 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \e_in + connect \B \clz + connect \Y $9 + end + connect $8 $9 + process $group_4 + assign \e_out 13'0000000000000 + assign \e_out $8 [12:0] + sync init + end + process $group_5 + assign \m_out 53'00000000000000000000000000000000000000000000000000000 + assign \m_out \temp + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.align.norm_pe_b.pe" +module \pe__4 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75" + wire width 53 input 0 \i + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 6 output 1 \o + process $group_0 + assign \o 6'000000 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [52] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [51] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [50] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [49] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [48] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [47] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [46] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [45] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [44] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [43] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [42] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [41] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [40] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [39] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [38] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [37] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [36] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [35] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [34] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [33] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [32] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [31] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [30] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [29] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [28] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [27] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [26] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [25] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [24] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [23] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [22] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [21] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [20] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [19] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [18] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [17] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [16] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [15] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [14] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [13] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [12] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [11] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [10] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [9] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [8] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000000 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77" + wire width 1 \n + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.align.norm_pe_b" +module \norm_pe_b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31" + wire width 53 input 0 \m_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32" + wire width 13 input 1 \e_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34" + wire width 13 output 2 \e_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33" + wire width 53 output 3 \m_out + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75" + wire width 53 \pe_i + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 6 \pe_o + cell \pe__4 \pe + connect \i \pe_i + connect \o \pe_o + end + process $group_0 + assign \pe_i 53'00000000000000000000000000000000000000000000000000000 + assign \pe_i { \m_in [0] \m_in [1] \m_in [2] \m_in [3] \m_in [4] \m_in [5] \m_in [6] \m_in [7] \m_in [8] \m_in [9] \m_in [10] \m_in [11] \m_in [12] \m_in [13] \m_in [14] \m_in [15] \m_in [16] \m_in [17] \m_in [18] \m_in [19] \m_in [20] \m_in [21] \m_in [22] \m_in [23] \m_in [24] \m_in [25] \m_in [26] \m_in [27] \m_in [28] \m_in [29] \m_in [30] \m_in [31] \m_in [32] \m_in [33] \m_in [34] \m_in [35] \m_in [36] \m_in [37] \m_in [38] \m_in [39] \m_in [40] \m_in [41] \m_in [42] \m_in [43] \m_in [44] \m_in [45] \m_in [46] \m_in [47] \m_in [48] \m_in [49] \m_in [50] \m_in [51] \m_in [52] } + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:48" + wire width 13 \clz + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 13 $1 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + cell $pos $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'110 + parameter \Y_WIDTH 4'1101 + connect \A \pe_o + connect \Y $1 + end + process $group_1 + assign \clz 13'0000000000000 + assign \clz $1 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:50" + wire width 13 \uclz + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 13 $3 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + cell $pos $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'110 + parameter \Y_WIDTH 4'1101 + connect \A \pe_o + connect \Y $3 + end + process $group_2 + assign \uclz 13'0000000000000 + assign \uclz $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:51" + wire width 53 \temp + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + wire width 8244 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + wire width 8244 $6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + cell $sshl $7 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 14'10000000110100 + connect \A \m_in + connect \B \uclz + connect \Y $6 + end + connect $5 $6 + process $group_3 + assign \temp 53'00000000000000000000000000000000000000000000000000000 + assign \temp $5 [52:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + wire width 14 $8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + wire width 14 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + cell $sub $10 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \e_in + connect \B \clz + connect \Y $9 + end + connect $8 $9 + process $group_4 + assign \e_out 13'0000000000000 + assign \e_out $8 [12:0] + sync init + end + process $group_5 + assign \m_out 53'00000000000000000000000000000000000000000000000000000 + assign \m_out \temp + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm.align" +module \align + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 input 0 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 input 1 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 2 \a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 3 \a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 4 \i_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 5 \b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 6 \b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 7 \i_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 8 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 9 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 output 10 \out_do_z__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 output 11 \oz__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 12 \a_s__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 13 \a_e__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 14 \o_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 15 \b_s__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 16 \b_e__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 17 \o_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 18 \muxid__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 19 \op__8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \norm1_insel_a_m_msbzero + cell \norm1_insel_a \norm1_insel_a + connect \a_e \a_e + connect \i_a_m \i_a_m + connect \m_msbzero \norm1_insel_a_m_msbzero + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \norm1_insel_b_m_msbzero + cell \norm1_insel_b \norm1_insel_b + connect \b_e \b_e + connect \i_b_m \i_b_m + connect \m_msbzero \norm1_insel_b_m_msbzero + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31" + wire width 53 \norm_pe_a_m_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32" + wire width 13 \norm_pe_a_e_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34" + wire width 13 \norm_pe_a_e_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33" + wire width 53 \norm_pe_a_m_out + cell \norm_pe_a \norm_pe_a + connect \m_in \norm_pe_a_m_in + connect \e_in \norm_pe_a_e_in + connect \e_out \norm_pe_a_e_out + connect \m_out \norm_pe_a_m_out + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31" + wire width 53 \norm_pe_b_m_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32" + wire width 13 \norm_pe_b_e_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34" + wire width 13 \norm_pe_b_e_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33" + wire width 53 \norm_pe_b_m_out + cell \norm_pe_b \norm_pe_b + connect \m_in \norm_pe_b_m_in + connect \e_in \norm_pe_b_e_in + connect \e_out \norm_pe_b_e_out + connect \m_out \norm_pe_b_m_out + end + process $group_0 + assign \norm_pe_a_m_in 53'00000000000000000000000000000000000000000000000000000 + assign \norm_pe_a_m_in \i_a_m + sync init + end + process $group_1 + assign \norm_pe_a_e_in 13'0000000000000 + assign \norm_pe_a_e_in \a_e + sync init + end + process $group_2 + assign \norm_pe_b_m_in 53'00000000000000000000000000000000000000000000000000000 + assign \norm_pe_b_m_in \i_b_m + sync init + end + process $group_3 + assign \norm_pe_b_e_in 13'0000000000000 + assign \norm_pe_b_e_in \b_e + sync init + end + process $group_4 + assign \a_s__3 1'0 + assign \a_s__3 \a_s + sync init + end + process $group_5 + assign \b_s__5 1'0 + assign \b_s__5 \b_s + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:60" + wire width 1 \decrease_a + process $group_6 + assign \decrease_a 1'0 + assign \decrease_a \norm1_insel_a_m_msbzero + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:61" + wire width 1 \decrease_b + process $group_7 + assign \decrease_b 1'0 + assign \decrease_b \norm1_insel_b_m_msbzero + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:67" + wire width 13 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:67" + cell $mux $10 + parameter \WIDTH 4'1101 + connect \A \a_e + connect \B \norm_pe_a_e_out + connect \S \decrease_a + connect \Y $9 + end + process $group_8 + assign \a_e__4 13'0000000000000 + assign \a_e__4 $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:68" + wire width 53 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:68" + cell $mux $12 + parameter \WIDTH 6'110101 + connect \A \i_a_m + connect \B \norm_pe_a_m_out + connect \S \decrease_a + connect \Y $11 + end + process $group_9 + assign \o_a_m 53'00000000000000000000000000000000000000000000000000000 + assign \o_a_m $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:71" + wire width 13 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:71" + cell $mux $14 + parameter \WIDTH 4'1101 + connect \A \b_e + connect \B \norm_pe_b_e_out + connect \S \decrease_b + connect \Y $13 + end + process $group_10 + assign \b_e__6 13'0000000000000 + assign \b_e__6 $13 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:72" + wire width 53 $15 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/align.py:72" + cell $mux $16 + parameter \WIDTH 6'110101 + connect \A \i_b_m + connect \B \norm_pe_b_m_out + connect \S \decrease_b + connect \Y $15 + end + process $group_11 + assign \o_b_m 53'00000000000000000000000000000000000000000000000000000 + assign \o_b_m $15 + sync init + end + process $group_12 + assign \muxid__7 2'00 + assign \muxid__7 \muxid + sync init + end + process $group_13 + assign \op__8 0'0 + assign \op__8 \op + sync init + end + process $group_14 + assign \out_do_z__1 1'0 + assign \out_do_z__1 \out_do_z + sync init + end + process $group_15 + assign \oz__2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__2 \oz + sync init + end + connect \op__8 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.scnorm" +module \scnorm + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 2 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 3 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \z_e$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 4 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \z_m$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 output 5 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \out_do_z$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 output 6 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \oz$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 7 \a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \a_s$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 8 \a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \a_e$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 9 \a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \a_m$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 10 \b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \b_s$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 11 \b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \b_e$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 12 \b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \b_m$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 13 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 14 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op$next + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 15 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 16 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 17 \a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 18 \b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 19 \c + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 20 \muxid__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 21 \op__2 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 22 \rst + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 23 \clk + cell \p__2 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n__3 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \specialcases_a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \specialcases_b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \specialcases_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \specialcases_op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \specialcases_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \specialcases_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \specialcases_a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \specialcases_a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \specialcases_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \specialcases_b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \specialcases_b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \specialcases_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \specialcases_muxid__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \specialcases_op__4 + cell \specialcases \specialcases + connect \a \specialcases_a + connect \b \specialcases_b + connect \muxid \specialcases_muxid + connect \op \specialcases_op + connect \out_do_z \specialcases_out_do_z + connect \oz \specialcases_oz + connect \a_s \specialcases_a_s + connect \a_e \specialcases_a_e + connect \a_m \specialcases_a_m + connect \b_s \specialcases_b_s + connect \b_e \specialcases_b_e + connect \b_m \specialcases_b_m + connect \muxid__1 \specialcases_muxid__3 + connect \op__2 \specialcases_op__4 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \denormalise_z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \denormalise_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \denormalise_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \denormalise_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \denormalise_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \denormalise_a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \denormalise_a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \denormalise_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \denormalise_b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \denormalise_b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \denormalise_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \denormalise_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \denormalise_op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \denormalise_z_s__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \denormalise_z_e__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \denormalise_z_m__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \denormalise_out_do_z__8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \denormalise_oz__9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \denormalise_a_s__10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \denormalise_a_e__11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \denormalise_a_m__12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \denormalise_b_s__13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \denormalise_b_e__14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \denormalise_b_m__15 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \denormalise_muxid__16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \denormalise_op__17 + cell \denormalise \denormalise + connect \z_s \denormalise_z_s + connect \z_e \denormalise_z_e + connect \z_m \denormalise_z_m + connect \out_do_z \denormalise_out_do_z + connect \oz \denormalise_oz + connect \a_s \denormalise_a_s + connect \a_e \denormalise_a_e + connect \a_m \denormalise_a_m + connect \b_s \denormalise_b_s + connect \b_e \denormalise_b_e + connect \b_m \denormalise_b_m + connect \muxid \denormalise_muxid + connect \op \denormalise_op + connect \z_s__1 \denormalise_z_s__5 + connect \z_e__2 \denormalise_z_e__6 + connect \z_m__3 \denormalise_z_m__7 + connect \out_do_z__4 \denormalise_out_do_z__8 + connect \oz__5 \denormalise_oz__9 + connect \a_s__6 \denormalise_a_s__10 + connect \a_e__7 \denormalise_a_e__11 + connect \a_m__8 \denormalise_a_m__12 + connect \b_s__9 \denormalise_b_s__13 + connect \b_e__10 \denormalise_b_e__14 + connect \b_m__11 \denormalise_b_m__15 + connect \muxid__12 \denormalise_muxid__16 + connect \op__13 \denormalise_op__17 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \align_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \align_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \align_a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \align_a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \align_i_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \align_b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \align_b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \align_i_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \align_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \align_op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \align_out_do_z__18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \align_oz__19 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \align_a_s__20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \align_a_e__21 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \align_o_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \align_b_s__22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \align_b_e__23 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \align_o_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \align_muxid__24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \align_op__25 + cell \align \align + connect \out_do_z \align_out_do_z + connect \oz \align_oz + connect \a_s \align_a_s + connect \a_e \align_a_e + connect \i_a_m \align_i_a_m + connect \b_s \align_b_s + connect \b_e \align_b_e + connect \i_b_m \align_i_b_m + connect \muxid \align_muxid + connect \op \align_op + connect \out_do_z__1 \align_out_do_z__18 + connect \oz__2 \align_oz__19 + connect \a_s__3 \align_a_s__20 + connect \a_e__4 \align_a_e__21 + connect \o_a_m \align_o_a_m + connect \b_s__5 \align_b_s__22 + connect \b_e__6 \align_b_e__23 + connect \o_b_m \align_o_b_m + connect \muxid__7 \align_muxid__24 + connect \op__8 \align_op__25 + end + process $group_0 + assign \specialcases_a 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \specialcases_a \a + sync init + end + process $group_1 + assign \specialcases_b 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \specialcases_b \b + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \c__26 + process $group_2 + assign \c__26 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \c__26 \c + sync init + end + process $group_3 + assign \specialcases_muxid 2'00 + assign \specialcases_muxid \muxid__1 + sync init + end + process $group_4 + assign \specialcases_op 0'0 + assign \specialcases_op \op__2 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s__27 + process $group_5 + assign \denormalise_z_s 1'0 + assign \denormalise_z_s \z_s__27 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \z_e__28 + process $group_6 + assign \denormalise_z_e 13'0000000000000 + assign \denormalise_z_e \z_e__28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \z_m__29 + process $group_7 + assign \denormalise_z_m 53'00000000000000000000000000000000000000000000000000000 + assign \denormalise_z_m \z_m__29 + sync init + end + process $group_8 + assign \denormalise_out_do_z 1'0 + assign \denormalise_out_do_z \specialcases_out_do_z + sync init + end + process $group_9 + assign \denormalise_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \denormalise_oz \specialcases_oz + sync init + end + process $group_10 + assign \denormalise_a_s 1'0 + assign \denormalise_a_s \specialcases_a_s + sync init + end + process $group_11 + assign \denormalise_a_e 13'0000000000000 + assign \denormalise_a_e \specialcases_a_e + sync init + end + process $group_12 + assign \denormalise_a_m 53'00000000000000000000000000000000000000000000000000000 + assign \denormalise_a_m \specialcases_a_m + sync init + end + process $group_13 + assign \denormalise_b_s 1'0 + assign \denormalise_b_s \specialcases_b_s + sync init + end + process $group_14 + assign \denormalise_b_e 13'0000000000000 + assign \denormalise_b_e \specialcases_b_e + sync init + end + process $group_15 + assign \denormalise_b_m 53'00000000000000000000000000000000000000000000000000000 + assign \denormalise_b_m \specialcases_b_m + sync init + end + process $group_16 + assign \denormalise_muxid 2'00 + assign \denormalise_muxid \specialcases_muxid__3 + sync init + end + process $group_17 + assign \denormalise_op 0'0 + assign \denormalise_op \specialcases_op__4 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s__30 + process $group_18 + assign \z_s__30 1'0 + assign \z_s__30 \denormalise_z_s__5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \z_e__31 + process $group_19 + assign \z_e__31 13'0000000000000 + assign \z_e__31 \denormalise_z_e__6 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \z_m__32 + process $group_20 + assign \z_m__32 53'00000000000000000000000000000000000000000000000000000 + assign \z_m__32 \denormalise_z_m__7 + sync init + end + process $group_21 + assign \align_out_do_z 1'0 + assign \align_out_do_z \denormalise_out_do_z__8 + sync init + end + process $group_22 + assign \align_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \align_oz \denormalise_oz__9 + sync init + end + process $group_23 + assign \align_a_s 1'0 + assign \align_a_s \denormalise_a_s__10 + sync init + end + process $group_24 + assign \align_a_e 13'0000000000000 + assign \align_a_e \denormalise_a_e__11 + sync init + end + process $group_25 + assign \align_i_a_m 53'00000000000000000000000000000000000000000000000000000 + assign \align_i_a_m \denormalise_a_m__12 + sync init + end + process $group_26 + assign \align_b_s 1'0 + assign \align_b_s \denormalise_b_s__13 + sync init + end + process $group_27 + assign \align_b_e 13'0000000000000 + assign \align_b_e \denormalise_b_e__14 + sync init + end + process $group_28 + assign \align_i_b_m 53'00000000000000000000000000000000000000000000000000000 + assign \align_i_b_m \denormalise_b_m__15 + sync init + end + process $group_29 + assign \align_muxid 2'00 + assign \align_muxid \denormalise_muxid__16 + sync init + end + process $group_30 + assign \align_op 0'0 + assign \align_op \denormalise_op__17 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i__33 + process $group_31 + assign \p_valid_i__33 1'0 + assign \p_valid_i__33 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_32 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $34 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624" + cell $and $35 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__33 + connect \B \p_ready_o + connect \Y $34 + end + process $group_33 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $34 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s__36 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s__37 + process $group_34 + assign \z_s__36 1'0 + assign \z_s__36 \z_s__37 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \z_e__38 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \z_e__39 + process $group_35 + assign \z_e__38 13'0000000000000 + assign \z_e__38 \z_e__39 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \z_m__40 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \z_m__41 + process $group_36 + assign \z_m__40 53'00000000000000000000000000000000000000000000000000000 + assign \z_m__40 \z_m__41 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \out_do_z__42 + process $group_37 + assign \out_do_z__42 1'0 + assign \out_do_z__42 \align_out_do_z__18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \oz__43 + process $group_38 + assign \oz__43 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__43 \align_oz__19 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \a_s__44 + process $group_39 + assign \a_s__44 1'0 + assign \a_s__44 \align_a_s__20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \a_e__45 + process $group_40 + assign \a_e__45 13'0000000000000 + assign \a_e__45 \align_a_e__21 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \a_m__46 + process $group_41 + assign \a_m__46 53'00000000000000000000000000000000000000000000000000000 + assign \a_m__46 \align_o_a_m + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \b_s__47 + process $group_42 + assign \b_s__47 1'0 + assign \b_s__47 \align_b_s__22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \b_e__48 + process $group_43 + assign \b_e__48 13'0000000000000 + assign \b_e__48 \align_b_e__23 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \b_m__49 + process $group_44 + assign \b_m__49 53'00000000000000000000000000000000000000000000000000000 + assign \b_m__49 \align_o_b_m + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__50 + process $group_45 + assign \muxid__50 2'00 + assign \muxid__50 \align_muxid__24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__51 + process $group_46 + assign \op__51 0'0 + assign \op__51 \align_op__25 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_47 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/xfrm.py:528" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_48 + assign \z_s$next \z_s + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \z_s$next \z_s__36 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \z_s$next \z_s__36 + end + sync init + update \z_s 1'0 + sync posedge \clk + update \z_s \z_s$next + end + process $group_49 + assign \z_e$next \z_e + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \z_e$next \z_e__38 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \z_e$next \z_e__38 + end + sync init + update \z_e 13'0000000000000 + sync posedge \clk + update \z_e \z_e$next + end + process $group_50 + assign \z_m$next \z_m + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \z_m$next \z_m__40 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \z_m$next \z_m__40 + end + sync init + update \z_m 53'00000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \z_m \z_m$next + end + process $group_51 + assign \out_do_z$next \out_do_z + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \out_do_z$next \out_do_z__42 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \out_do_z$next \out_do_z__42 + end + sync init + update \out_do_z 1'0 + sync posedge \clk + update \out_do_z \out_do_z$next + end + process $group_52 + assign \oz$next \oz + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \oz$next \oz__43 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \oz$next \oz__43 + end + sync init + update \oz 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \oz \oz$next + end + process $group_53 + assign \a_s$next \a_s + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \a_s$next \a_s__44 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \a_s$next \a_s__44 + end + sync init + update \a_s 1'0 + sync posedge \clk + update \a_s \a_s$next + end + process $group_54 + assign \a_e$next \a_e + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \a_e$next \a_e__45 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \a_e$next \a_e__45 + end + sync init + update \a_e 13'0000000000000 + sync posedge \clk + update \a_e \a_e$next + end + process $group_55 + assign \a_m$next \a_m + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \a_m$next \a_m__46 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \a_m$next \a_m__46 + end + sync init + update \a_m 53'00000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \a_m \a_m$next + end + process $group_56 + assign \b_s$next \b_s + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \b_s$next \b_s__47 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \b_s$next \b_s__47 + end + sync init + update \b_s 1'0 + sync posedge \clk + update \b_s \b_s$next + end + process $group_57 + assign \b_e$next \b_e + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \b_e$next \b_e__48 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \b_e$next \b_e__48 + end + sync init + update \b_e 13'0000000000000 + sync posedge \clk + update \b_e \b_e$next + end + process $group_58 + assign \b_m$next \b_m + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \b_m$next \b_m__49 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \b_m$next \b_m__49 + end + sync init + update \b_m 53'00000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \b_m \b_m$next + end + process $group_59 + assign \muxid$next \muxid + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid$next \muxid__50 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid$next \muxid__50 + end + sync init + update \muxid 2'00 + sync posedge \clk + update \muxid \muxid$next + end + process $group_60 + assign \op$next \op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \op$next \op__51 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \op$next \op__51 + end + sync init + update \op 0'0 + sync posedge \clk + update \op \op$next + end + process $group_61 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_62 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \op 0'0 + connect \specialcases_op 0'0 + connect \denormalise_op 0'0 + connect \align_op 0'0 + connect \z_s__27 1'0 + connect \z_e__28 13'0000000000000 + connect \z_m__29 53'00000000000000000000000000000000000000000000000000000 + connect \z_s__37 1'0 + connect \z_e__39 13'0000000000000 + connect \z_m__41 53'00000000000000000000000000000000000000000000000000000 + connect \op__51 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.mulstages.p" +module \p__5 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.mulstages.n" +module \n__6 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.mulstages.mul0" +module \mul0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 input 0 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 input 1 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 2 \a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 3 \a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 4 \a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 5 \b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 6 \b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 7 \b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 8 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 9 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 10 \s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 11 \e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:18" + wire width 1 output 12 \out_do_z__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:19" + wire width 64 output 13 \oz__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21" + wire width 108 output 14 \product + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 15 \muxid__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 16 \op__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:33" + wire width 54 \am0 + process $group_0 + assign \am0 54'000000000000000000000000000000000000000000000000000000 + assign \am0 { 1'0 \a_m } + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:34" + wire width 54 \bm0 + process $group_1 + assign \bm0 54'000000000000000000000000000000000000000000000000000000 + assign \bm0 { 1'0 \b_m } + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39" + wire width 15 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39" + wire width 14 $6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39" + cell $add $7 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \a_e + connect \B \b_e + connect \Y $6 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39" + wire width 15 $8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:39" + cell $add $9 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1110 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1110 + parameter \Y_WIDTH 4'1111 + connect \A $6 + connect \B 14'00000000000001 + connect \Y $8 + end + connect $5 $8 + process $group_2 + assign \e 13'0000000000000 + assign \e $5 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40" + wire width 111 $10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40" + wire width 108 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40" + cell $mul $12 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110110 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110110 + parameter \Y_WIDTH 7'1101100 + connect \A \am0 + connect \B \bm0 + connect \Y $11 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40" + wire width 111 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:40" + cell $mul $14 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 7'1101100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 2'11 + parameter \Y_WIDTH 7'1101111 + connect \A $11 + connect \B 3'100 + connect \Y $13 + end + connect $10 $13 + process $group_3 + assign \product 108'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \product $10 [107:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:41" + wire width 1 $15 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul0.py:41" + cell $xor $16 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \a_s + connect \B \b_s + connect \Y $15 + end + process $group_4 + assign \s 1'0 + assign \s $15 + sync init + end + process $group_5 + assign \oz__2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__2 \oz + sync init + end + process $group_6 + assign \out_do_z__1 1'0 + assign \out_do_z__1 \out_do_z + sync init + end + process $group_7 + assign \muxid__3 2'00 + assign \muxid__3 \muxid + sync init + end + process $group_8 + assign \op__4 0'0 + assign \op__4 \op + sync init + end + connect \op__4 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.mulstages.mul1" +module \mul1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 0 \s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 1 \e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:18" + wire width 1 input 2 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:19" + wire width 64 input 3 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21" + wire width 108 input 4 \product + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 5 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 6 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 7 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 8 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 9 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 output 10 \out_do_z__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 output 11 \oz__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 output 12 \guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 output 13 \round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 output 14 \sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 output 15 \m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 16 \muxid__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 17 \op__4 + process $group_0 + assign \z_s 1'0 + assign \z_s \s + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:40" + wire width 1 \msb + process $group_1 + assign \msb 1'0 + assign \msb \product [107] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:39" + wire width 108 \p + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43" + wire width 109 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21" + wire width 109 $6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21" + cell $pos $7 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 7'1101100 + parameter \Y_WIDTH 7'1101101 + connect \A \product + connect \Y $6 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43" + wire width 109 $8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43" + cell $sshl $9 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 7'1101100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 7'1101101 + connect \A \product + connect \B 1'1 + connect \Y $8 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43" + wire width 109 $10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:43" + cell $mux $11 + parameter \WIDTH 7'1101101 + connect \A $8 + connect \B $6 + connect \S \msb + connect \Y $10 + end + connect $5 $10 + process $group_2 + assign \p 108'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \p $5 [107:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44" + wire width 14 $12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + cell $pos $14 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \e + connect \Y $13 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44" + wire width 14 $15 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44" + cell $sub $16 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \e + connect \B 13'0000000000001 + connect \Y $15 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44" + wire width 14 $17 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:44" + cell $mux $18 + parameter \WIDTH 4'1110 + connect \A $15 + connect \B $13 + connect \S \msb + connect \Y $17 + end + connect $12 $17 + process $group_3 + assign \z_e 13'0000000000000 + assign \z_e $12 [12:0] + sync init + end + process $group_4 + assign \z_m 53'00000000000000000000000000000000000000000000000000000 + assign \z_m \p [107:55] + sync init + end + process $group_5 + assign \m0 1'0 + assign \m0 \p [55] + sync init + end + process $group_6 + assign \guard 1'0 + assign \guard \p [54] + sync init + end + process $group_7 + assign \round 1'0 + assign \round \p [53] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:54" + wire width 1 $19 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/mul1.py:54" + cell $reduce_bool $20 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \p [52:0] + connect \Y $19 + end + process $group_8 + assign \sticky 1'0 + assign \sticky $19 + sync init + end + process $group_9 + assign \out_do_z__1 1'0 + assign \out_do_z__1 \out_do_z + sync init + end + process $group_10 + assign \oz__2 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__2 \oz + sync init + end + process $group_11 + assign \muxid__3 2'00 + assign \muxid__3 \muxid + sync init + end + process $group_12 + assign \op__4 0'0 + assign \op__4 \op + sync init + end + connect \op__4 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.mulstages" +module \mulstages + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 2 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 3 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 4 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 input 5 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 input 6 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 7 \a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 8 \a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 9 \a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 10 \b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 11 \b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 12 \b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 13 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 14 \op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 15 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 16 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 17 \z_s__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s__1$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 18 \z_e__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \z_e__2$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 19 \z_m__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \z_m__3$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 output 20 \out_do_z__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 \out_do_z__4$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 output 21 \oz__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 \oz__5$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 output 22 \guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 \guard$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 output 23 \round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 \round$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 output 24 \sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 \sticky$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 output 25 \m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 \m0$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 output 26 \fflags + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 \fflags$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 27 \muxid__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__6$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 28 \op__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__7$next + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 29 \rst + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 30 \clk + cell \p__5 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n__6 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \mul0_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \mul0_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mul0_a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mul0_a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \mul0_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mul0_b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mul0_b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \mul0_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \mul0_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \mul0_op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mul0_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mul0_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:18" + wire width 1 \mul0_out_do_z__8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:19" + wire width 64 \mul0_oz__9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21" + wire width 108 \mul0_product + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \mul0_muxid__10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \mul0_op__11 + cell \mul0 \mul0 + connect \out_do_z \mul0_out_do_z + connect \oz \mul0_oz + connect \a_s \mul0_a_s + connect \a_e \mul0_a_e + connect \a_m \mul0_a_m + connect \b_s \mul0_b_s + connect \b_e \mul0_b_e + connect \b_m \mul0_b_m + connect \muxid \mul0_muxid + connect \op \mul0_op + connect \s \mul0_s + connect \e \mul0_e + connect \out_do_z__1 \mul0_out_do_z__8 + connect \oz__2 \mul0_oz__9 + connect \product \mul0_product + connect \muxid__3 \mul0_muxid__10 + connect \op__4 \mul0_op__11 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mul1_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mul1_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:18" + wire width 1 \mul1_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:19" + wire width 64 \mul1_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpmul/datastructs.py:21" + wire width 108 \mul1_product + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \mul1_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \mul1_op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mul1_z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mul1_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \mul1_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 \mul1_out_do_z__12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 \mul1_oz__13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 \mul1_guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 \mul1_round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 \mul1_sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 \mul1_m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \mul1_muxid__14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \mul1_op__15 + cell \mul1 \mul1 + connect \s \mul1_s + connect \e \mul1_e + connect \out_do_z \mul1_out_do_z + connect \oz \mul1_oz + connect \product \mul1_product + connect \muxid \mul1_muxid + connect \op \mul1_op + connect \z_s \mul1_z_s + connect \z_e \mul1_z_e + connect \z_m \mul1_z_m + connect \out_do_z__1 \mul1_out_do_z__12 + connect \oz__2 \mul1_oz__13 + connect \guard \mul1_guard + connect \round \mul1_round + connect \sticky \mul1_sticky + connect \m0 \mul1_m0 + connect \muxid__3 \mul1_muxid__14 + connect \op__4 \mul1_op__15 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s__16 + process $group_0 + assign \z_s__16 1'0 + assign \z_s__16 \z_s + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \z_e__17 + process $group_1 + assign \z_e__17 13'0000000000000 + assign \z_e__17 \z_e + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \z_m__18 + process $group_2 + assign \z_m__18 53'00000000000000000000000000000000000000000000000000000 + assign \z_m__18 \z_m + sync init + end + process $group_3 + assign \mul0_out_do_z 1'0 + assign \mul0_out_do_z \out_do_z + sync init + end + process $group_4 + assign \mul0_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul0_oz \oz + sync init + end + process $group_5 + assign \mul0_a_s 1'0 + assign \mul0_a_s \a_s + sync init + end + process $group_6 + assign \mul0_a_e 13'0000000000000 + assign \mul0_a_e \a_e + sync init + end + process $group_7 + assign \mul0_a_m 53'00000000000000000000000000000000000000000000000000000 + assign \mul0_a_m \a_m + sync init + end + process $group_8 + assign \mul0_b_s 1'0 + assign \mul0_b_s \b_s + sync init + end + process $group_9 + assign \mul0_b_e 13'0000000000000 + assign \mul0_b_e \b_e + sync init + end + process $group_10 + assign \mul0_b_m 53'00000000000000000000000000000000000000000000000000000 + assign \mul0_b_m \b_m + sync init + end + process $group_11 + assign \mul0_muxid 2'00 + assign \mul0_muxid \muxid + sync init + end + process $group_12 + assign \mul0_op 0'0 + assign \mul0_op \op + sync init + end + process $group_13 + assign \mul1_s 1'0 + assign \mul1_s \mul0_s + sync init + end + process $group_14 + assign \mul1_e 13'0000000000000 + assign \mul1_e \mul0_e + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \m__19 + process $group_15 + assign \m 53'00000000000000000000000000000000000000000000000000000 + assign \m \m__19 + sync init + end + process $group_16 + assign \mul1_out_do_z 1'0 + assign \mul1_out_do_z \mul0_out_do_z__8 + sync init + end + process $group_17 + assign \mul1_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mul1_oz \mul0_oz__9 + sync init + end + process $group_18 + assign \mul1_product 108'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign \mul1_product \mul0_product + sync init + end + process $group_19 + assign \mul1_muxid 2'00 + assign \mul1_muxid \mul0_muxid__10 + sync init + end + process $group_20 + assign \mul1_op 0'0 + assign \mul1_op \mul0_op__11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i__20 + process $group_21 + assign \p_valid_i__20 1'0 + assign \p_valid_i__20 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_22 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $21 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624" + cell $and $22 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__20 + connect \B \p_ready_o + connect \Y $21 + end + process $group_23 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $21 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s__23 + process $group_24 + assign \z_s__23 1'0 + assign \z_s__23 \mul1_z_s + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \z_e__24 + process $group_25 + assign \z_e__24 13'0000000000000 + assign \z_e__24 \mul1_z_e + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \z_m__25 + process $group_26 + assign \z_m__25 53'00000000000000000000000000000000000000000000000000000 + assign \z_m__25 \mul1_z_m + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 \out_do_z__26 + process $group_27 + assign \out_do_z__26 1'0 + assign \out_do_z__26 \mul1_out_do_z__12 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 \oz__27 + process $group_28 + assign \oz__27 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__27 \mul1_oz__13 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 \guard__28 + process $group_29 + assign \guard__28 1'0 + assign \guard__28 \mul1_guard + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 \round__29 + process $group_30 + assign \round__29 1'0 + assign \round__29 \mul1_round + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 \sticky__30 + process $group_31 + assign \sticky__30 1'0 + assign \sticky__30 \mul1_sticky + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 \m0__31 + process $group_32 + assign \m0__31 1'0 + assign \m0__31 \mul1_m0 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 \fflags__32 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 \fflags__33 + process $group_33 + assign \fflags__32 5'00000 + assign \fflags__32 \fflags__33 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__34 + process $group_34 + assign \muxid__34 2'00 + assign \muxid__34 \mul1_muxid__14 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__35 + process $group_35 + assign \op__35 0'0 + assign \op__35 \mul1_op__15 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_36 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/xfrm.py:528" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_37 + assign \z_s__1$next \z_s__1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \z_s__1$next \z_s__23 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \z_s__1$next \z_s__23 + end + sync init + update \z_s__1 1'0 + sync posedge \clk + update \z_s__1 \z_s__1$next + end + process $group_38 + assign \z_e__2$next \z_e__2 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \z_e__2$next \z_e__24 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \z_e__2$next \z_e__24 + end + sync init + update \z_e__2 13'0000000000000 + sync posedge \clk + update \z_e__2 \z_e__2$next + end + process $group_39 + assign \z_m__3$next \z_m__3 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \z_m__3$next \z_m__25 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \z_m__3$next \z_m__25 + end + sync init + update \z_m__3 53'00000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \z_m__3 \z_m__3$next + end + process $group_40 + assign \out_do_z__4$next \out_do_z__4 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \out_do_z__4$next \out_do_z__26 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \out_do_z__4$next \out_do_z__26 + end + sync init + update \out_do_z__4 1'0 + sync posedge \clk + update \out_do_z__4 \out_do_z__4$next + end + process $group_41 + assign \oz__5$next \oz__5 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \oz__5$next \oz__27 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \oz__5$next \oz__27 + end + sync init + update \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \oz__5 \oz__5$next + end + process $group_42 + assign \guard$next \guard + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \guard$next \guard__28 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \guard$next \guard__28 + end + sync init + update \guard 1'0 + sync posedge \clk + update \guard \guard$next + end + process $group_43 + assign \round$next \round + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \round$next \round__29 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \round$next \round__29 + end + sync init + update \round 1'0 + sync posedge \clk + update \round \round$next + end + process $group_44 + assign \sticky$next \sticky + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \sticky$next \sticky__30 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \sticky$next \sticky__30 + end + sync init + update \sticky 1'0 + sync posedge \clk + update \sticky \sticky$next + end + process $group_45 + assign \m0$next \m0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \m0$next \m0__31 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \m0$next \m0__31 + end + sync init + update \m0 1'0 + sync posedge \clk + update \m0 \m0$next + end + process $group_46 + assign \fflags$next \fflags + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \fflags$next \fflags__32 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \fflags$next \fflags__32 + end + sync init + update \fflags 5'00000 + sync posedge \clk + update \fflags \fflags$next + end + process $group_47 + assign \muxid__6$next \muxid__6 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid__6$next \muxid__34 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid__6$next \muxid__34 + end + sync init + update \muxid__6 2'00 + sync posedge \clk + update \muxid__6 \muxid__6$next + end + process $group_48 + assign \op__7$next \op__7 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \op__7$next \op__35 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \op__7$next \op__35 + end + sync init + update \op__7 0'0 + sync posedge \clk + update \op__7 \op__7$next + end + process $group_49 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_50 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \op__7 0'0 + connect \mul0_op 0'0 + connect \mul1_op 0'0 + connect \m__19 53'00000000000000000000000000000000000000000000000000000 + connect \fflags__33 5'00000 + connect \op__35 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.p" +module \p__7 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.n" +module \n__8 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm1_out_overflow" +module \norm1_out_overflow + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 input 0 \norm1of_guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 input 1 \norm1of_round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 input 2 \norm1of_sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 input 3 \norm1of_m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:921" + wire width 1 output 4 \norm1of_roundz_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913" + cell $or $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \norm1of_round + connect \B \norm1of_sticky + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913" + cell $or $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $1 + connect \B \norm1of_m0 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:913" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \norm1of_guard + connect \B $3 + connect \Y $5 + end + process $group_0 + assign \norm1of_roundz_out 1'0 + assign \norm1of_roundz_out $5 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm1_insel_z" +module \norm1_insel_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 0 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 1 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 output 2 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 output 3 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 output 4 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 output 5 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \z_e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \z_m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \z_m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm_exp.multishift_r" +module \multishift_r + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:557" + wire width 57 input 0 \inp + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:558" + wire width 13 input 1 \diff + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:556" + wire width 57 output 2 \m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:568" + wire width 13 \maxslen + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574" + wire width 14 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:558" + wire width 14 $2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:558" + cell $pos $3 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \diff + connect \Y $2 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574" + wire width 14 $4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574" + cell $gt $6 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \diff + connect \B 13'0000000111000 + connect \Y $5 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:574" + cell $mux $7 + parameter \WIDTH 4'1110 + connect \A $2 + connect \B 14'00000000111000 + connect \S $5 + connect \Y $4 + end + connect $1 $4 + process $group_0 + assign \maxslen 13'0000000000000 + assign \maxslen $1 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:569" + wire width 13 \maxsleni + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575" + wire width 15 $8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575" + wire width 15 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575" + cell $sub $10 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1111 + connect \A 13'0000000111000 + connect \B \diff + connect \Y $9 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575" + wire width 15 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575" + wire width 1 $12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575" + cell $gt $13 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \diff + connect \B 13'0000000111000 + connect \Y $12 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:575" + cell $mux $14 + parameter \WIDTH 4'1111 + connect \A $9 + connect \B 15'000000000000000 + connect \S $12 + connect \Y $11 + end + connect $8 $11 + process $group_1 + assign \maxsleni 13'0000000000000 + assign \maxsleni $8 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:564" + wire width 57 \rs + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223" + wire width 57 $15 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:319" + wire width 56 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:319" + cell $sshr $17 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 6'111000 + connect \A \inp [56:1] + connect \B \maxslen + connect \Y $16 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223" + cell $pos $18 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \Y_WIDTH 6'111001 + connect \A $16 + connect \Y $15 + end + process $group_2 + assign \rs 57'000000000000000000000000000000000000000000000000000000000 + assign \rs $15 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:565" + wire width 57 \m_mask + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223" + wire width 57 $19 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:581" + wire width 56 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:581" + cell $not $21 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \Y_WIDTH 6'111000 + connect \A 56'00000000000000000000000000000000000000000000000000000000 + connect \Y $20 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:319" + wire width 56 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:319" + cell $sshr $23 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 6'111000 + connect \A $20 + connect \B \maxsleni + connect \Y $22 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ast.py:223" + cell $pos $24 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \Y_WIDTH 6'111001 + connect \A $22 + connect \Y $19 + end + process $group_3 + assign \m_mask 57'000000000000000000000000000000000000000000000000000000000 + assign \m_mask $19 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:566" + wire width 57 \smask + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:582" + wire width 57 $25 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:582" + cell $and $26 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'111001 + parameter \Y_WIDTH 6'111001 + connect \A \inp [56:1] + connect \B \m_mask + connect \Y $25 + end + process $group_4 + assign \smask 57'000000000000000000000000000000000000000000000000000000000 + assign \smask $25 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:567" + wire width 1 \stickybit + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:584" + wire width 1 $27 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:584" + cell $reduce_bool $28 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111001 + parameter \Y_WIDTH 1'1 + connect \A \smask + connect \Y $27 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:584" + wire width 1 $29 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:584" + cell $or $30 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $27 + connect \B \inp [0] + connect \Y $29 + end + process $group_5 + assign \stickybit 1'0 + assign \stickybit $29 + sync init + end + process $group_6 + assign \m 57'000000000000000000000000000000000000000000000000000000000 + assign \m { \rs \stickybit } [56:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm_exp" +module \norm_exp + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:18" + wire width 57 input 0 \m_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:19" + wire width 13 input 1 \e_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:16" + wire width 13 input 2 \ediff + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:20" + wire width 57 output 3 \m_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:21" + wire width 13 output 4 \e_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:557" + wire width 57 \multishift_r_inp + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:558" + wire width 13 \multishift_r_diff + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:556" + wire width 57 \multishift_r_m + cell \multishift_r \multishift_r + connect \inp \multishift_r_inp + connect \diff \multishift_r_diff + connect \m \multishift_r_m + end + process $group_0 + assign \multishift_r_inp 57'000000000000000000000000000000000000000000000000000000000 + assign \multishift_r_inp \m_in + sync init + end + process $group_1 + assign \multishift_r_diff 13'0000000000000 + assign \multishift_r_diff \ediff + sync init + end + process $group_2 + assign \m_out 57'000000000000000000000000000000000000000000000000000000000 + assign \m_out \multishift_r_m + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:37" + wire width 14 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:37" + wire width 14 $2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:37" + cell $add $3 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \e_in + connect \B \ediff + connect \Y $2 + end + connect $1 $2 + process $group_3 + assign \e_out 13'0000000000000 + assign \e_out $1 [12:0] + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm_msb.pe" +module \pe__9 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75" + wire width 56 input 0 \i + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 6 output 1 \o + process $group_0 + assign \o 6'000000 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [55] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [54] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [53] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [52] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [51] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [50] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [49] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [48] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'110000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [47] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [46] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [45] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [44] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [43] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [42] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [41] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [40] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'101000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [39] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [38] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [37] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [36] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [35] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [34] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [33] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [32] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'100000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [31] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [30] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [29] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [28] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [27] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [26] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [25] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [24] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'011000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [23] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [22] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [21] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [20] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [19] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [18] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [17] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [16] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'010000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [15] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [14] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [13] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [12] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [11] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [10] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [9] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [8] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'001000 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [7] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000111 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [6] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000110 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [5] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000101 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [4] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000100 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [3] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000011 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [2] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000010 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [1] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000001 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + switch { \i [0] } + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:82" + case 1'1 + assign \o 6'000000 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:77" + wire width 1 \n + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:84" + cell $eq $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \i + connect \B 1'0 + connect \Y $1 + end + process $group_1 + assign \n 1'0 + assign \n $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.normalise_1.norm_msb" +module \norm_msb + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:29" + wire width 13 input 0 \limclz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31" + wire width 56 input 1 \m_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32" + wire width 13 input 2 \e_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33" + wire width 56 output 3 \m_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34" + wire width 13 output 4 \e_out + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:75" + wire width 56 \pe_i + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 6 \pe_o + cell \pe__9 \pe + connect \i \pe_i + connect \o \pe_o + end + process $group_0 + assign \pe_i 56'00000000000000000000000000000000000000000000000000000000 + assign \pe_i { \m_in [0] \m_in [1] \m_in [2] \m_in [3] \m_in [4] \m_in [5] \m_in [6] \m_in [7] \m_in [8] \m_in [9] \m_in [10] \m_in [11] \m_in [12] \m_in [13] \m_in [14] \m_in [15] \m_in [16] \m_in [17] \m_in [18] \m_in [19] \m_in [20] \m_in [21] \m_in [22] \m_in [23] \m_in [24] \m_in [25] \m_in [26] \m_in [27] \m_in [28] \m_in [29] \m_in [30] \m_in [31] \m_in [32] \m_in [33] \m_in [34] \m_in [35] \m_in [36] \m_in [37] \m_in [38] \m_in [39] \m_in [40] \m_in [41] \m_in [42] \m_in [43] \m_in [44] \m_in [45] \m_in [46] \m_in [47] \m_in [48] \m_in [49] \m_in [50] \m_in [51] \m_in [52] \m_in [53] \m_in [54] \m_in [55] } + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:48" + wire width 13 \clz + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 13 $1 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + cell $pos $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'110 + parameter \Y_WIDTH 4'1101 + connect \A \pe_o + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63" + wire width 13 $3 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 13 $4 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + cell $pos $5 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'110 + parameter \Y_WIDTH 4'1101 + connect \A \pe_o + connect \Y $4 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63" + wire width 1 $6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63" + cell $gt $7 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \limclz + connect \B $4 + connect \Y $6 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63" + cell $mux $8 + parameter \WIDTH 4'1101 + connect \A \limclz + connect \B $1 + connect \S $6 + connect \Y $3 + end + process $group_1 + assign \clz 13'0000000000000 + assign \clz $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:50" + wire width 13 \uclz + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 13 $9 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + cell $pos $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'110 + parameter \Y_WIDTH 4'1101 + connect \A \pe_o + connect \Y $9 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63" + wire width 13 $11 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + wire width 13 $12 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/lib/coding.py:76" + cell $pos $13 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'110 + parameter \Y_WIDTH 4'1101 + connect \A \pe_o + connect \Y $12 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63" + wire width 1 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63" + cell $gt $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \limclz + connect \B $12 + connect \Y $14 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:63" + cell $mux $16 + parameter \WIDTH 4'1101 + connect \A \limclz + connect \B $9 + connect \S $14 + connect \Y $11 + end + process $group_2 + assign \uclz 13'0000000000000 + assign \uclz $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:51" + wire width 56 \temp + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + wire width 8247 $17 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + wire width 8247 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:71" + cell $sshl $19 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 14'10000000110111 + connect \A \m_in + connect \B \uclz + connect \Y $18 + end + connect $17 $18 + process $group_3 + assign \temp 56'00000000000000000000000000000000000000000000000000000000 + assign \temp $17 [55:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + wire width 14 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + wire width 14 $21 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:72" + cell $sub $22 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \e_in + connect \B \clz + connect \Y $21 + end + connect $20 $21 + process $group_4 + assign \e_out 13'0000000000000 + assign \e_out $20 [12:0] + sync init + end + process $group_5 + assign \m_out 56'00000000000000000000000000000000000000000000000000000000 + assign \m_out \temp + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.normalise_1" +module \normalise_1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 0 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 1 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 2 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 input 3 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 input 4 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 input 5 \guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 input 6 \round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 input 7 \sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 input 8 \m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 input 9 \fflags + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 10 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 11 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 12 \z_s__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 13 \z_e__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 14 \z_m__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:25" + wire width 1 output 15 \out_do_z__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:26" + wire width 64 output 16 \oz__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:23" + wire width 1 output 17 \norm1_roundz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 18 \muxid__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 19 \op__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 \norm1_out_overflow_norm1of_guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 \norm1_out_overflow_norm1of_round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 \norm1_out_overflow_norm1of_sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 \norm1_out_overflow_norm1of_m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:921" + wire width 1 \norm1_out_overflow_norm1of_roundz_out + cell \norm1_out_overflow \norm1_out_overflow + connect \norm1of_guard \norm1_out_overflow_norm1of_guard + connect \norm1of_round \norm1_out_overflow_norm1of_round + connect \norm1of_sticky \norm1_out_overflow_norm1of_sticky + connect \norm1of_m0 \norm1_out_overflow_norm1of_m0 + connect \norm1of_roundz_out \norm1_out_overflow_norm1of_roundz_out + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \norm1_insel_z_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \norm1_insel_z_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \norm1_insel_z_m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \norm1_insel_z_exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \norm1_insel_z_exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \norm1_insel_z_exp_sub_n126 + cell \norm1_insel_z \norm1_insel_z + connect \z_e \norm1_insel_z_z_e + connect \z_m \norm1_insel_z_z_m + connect \m_msbzero \norm1_insel_z_m_msbzero + connect \exp_gt_n126 \norm1_insel_z_exp_gt_n126 + connect \exp_lt_n126 \norm1_insel_z_exp_lt_n126 + connect \exp_sub_n126 \norm1_insel_z_exp_sub_n126 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:18" + wire width 57 \norm_exp_m_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:19" + wire width 13 \norm_exp_e_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:16" + wire width 13 \norm_exp_ediff + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:20" + wire width 57 \norm_exp_m_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/exphigh.py:21" + wire width 13 \norm_exp_e_out + cell \norm_exp \norm_exp + connect \m_in \norm_exp_m_in + connect \e_in \norm_exp_e_in + connect \ediff \norm_exp_ediff + connect \m_out \norm_exp_m_out + connect \e_out \norm_exp_e_out + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:29" + wire width 13 \norm_msb_limclz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:31" + wire width 56 \norm_msb_m_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:32" + wire width 13 \norm_msb_e_in + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:33" + wire width 56 \norm_msb_m_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/msbhigh.py:34" + wire width 13 \norm_msb_e_out + cell \norm_msb \norm_msb + connect \limclz \norm_msb_limclz + connect \m_in \norm_msb_m_in + connect \e_in \norm_msb_e_in + connect \m_out \norm_msb_m_out + connect \e_out \norm_msb_e_out + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \z_s__8 + process $group_0 + assign \z_s__8 1'0 + assign \z_s__8 \z_s + sync init + end + process $group_1 + assign \norm1_insel_z_z_e 13'0000000000000 + assign \norm1_insel_z_z_e \z_e + sync init + end + process $group_2 + assign \norm1_insel_z_z_m 53'00000000000000000000000000000000000000000000000000000 + assign \norm1_insel_z_z_m \z_m + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 \out_do_z__9 + process $group_3 + assign \out_do_z__9 1'0 + assign \out_do_z__9 \out_do_z + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 \oz__10 + process $group_4 + assign \oz__10 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__10 \oz + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 \norm1_i_of_guard + process $group_5 + assign \norm1_i_of_guard 1'0 + assign \norm1_i_of_guard \guard + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 \norm1_i_of_roundbit + process $group_6 + assign \norm1_i_of_roundbit 1'0 + assign \norm1_i_of_roundbit \round + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 \norm1_i_of_sticky + process $group_7 + assign \norm1_i_of_sticky 1'0 + assign \norm1_i_of_sticky \sticky + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 \norm1_i_of_m0 + process $group_8 + assign \norm1_i_of_m0 1'0 + assign \norm1_i_of_m0 \m0 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 \fflags__11 + process $group_9 + assign \fflags__11 5'00000 + assign \fflags__11 \fflags + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__12 + process $group_10 + assign \muxid__12 2'00 + assign \muxid__12 \muxid + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__13 + process $group_11 + assign \op__13 0'0 + assign \op__13 \op + sync init + end + process $group_12 + assign \z_s__1 1'0 + assign \z_s__1 \z_s__8 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:75" + wire width 1 \decrease + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:76" + wire width 1 \increase + process $group_13 + assign \z_e__2 13'0000000000000 + assign \z_e__2 \norm1_insel_z_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + assign \z_e__2 \norm_msb_e_out + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \z_e__2 \norm_exp_e_out + end + sync init + end + process $group_14 + assign \z_m__3 53'00000000000000000000000000000000000000000000000000000 + assign \z_m__3 \norm1_insel_z_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + assign \z_m__3 \norm_msb_m_out [55:3] + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \z_m__3 \norm_exp_m_out [56:3] [52:0] + end + sync init + end + process $group_15 + assign \norm1_out_overflow_norm1of_guard 1'0 + assign \norm1_out_overflow_norm1of_guard \norm1_i_of_guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + assign \norm1_out_overflow_norm1of_guard \norm_msb_m_out [2] + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \norm1_out_overflow_norm1of_guard \norm_exp_m_out [2] + end + sync init + end + process $group_16 + assign \norm1_out_overflow_norm1of_round 1'0 + assign \norm1_out_overflow_norm1of_round \norm1_i_of_roundbit + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + assign \norm1_out_overflow_norm1of_round \norm_msb_m_out [1] + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \norm1_out_overflow_norm1of_round \norm_exp_m_out [1] + end + sync init + end + process $group_17 + assign \norm1_out_overflow_norm1of_sticky 1'0 + assign \norm1_out_overflow_norm1of_sticky \norm1_i_of_sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \norm1_out_overflow_norm1of_sticky \norm_exp_m_out [0] + end + sync init + end + process $group_18 + assign \norm1_out_overflow_norm1of_m0 1'0 + assign \norm1_out_overflow_norm1of_m0 \norm1_i_of_m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + assign \norm1_out_overflow_norm1of_m0 \norm_msb_m_out [3] + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \norm1_out_overflow_norm1of_m0 \norm_exp_m_out [3] + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 \norm1of_fflags + process $group_19 + assign \norm1of_fflags 5'00000 + assign \norm1of_fflags \fflags__11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:77" + wire width 1 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:77" + cell $and $15 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \norm1_insel_z_m_msbzero + connect \B \norm1_insel_z_exp_gt_n126 + connect \Y $14 + end + process $group_20 + assign \decrease 1'0 + assign \decrease $14 + sync init + end + process $group_21 + assign \increase 1'0 + assign \increase \norm1_insel_z_exp_lt_n126 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:82" + wire width 57 \temp_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:84" + wire width 57 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:84" + cell $pos $17 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'111000 + parameter \Y_WIDTH 6'111001 + connect \A { \norm1_insel_z_z_m \norm1_i_of_guard \norm1_i_of_roundbit \norm1_i_of_sticky } + connect \Y $16 + end + process $group_22 + assign \temp_m 57'000000000000000000000000000000000000000000000000000000000 + assign \temp_m $16 + sync init + end + process $group_23 + assign \norm_msb_limclz 13'0000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + assign \norm_msb_limclz \norm1_insel_z_exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + end + sync init + end + process $group_24 + assign \norm_msb_m_in 56'00000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + assign \norm_msb_m_in \temp_m [55:0] + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + end + sync init + end + process $group_25 + assign \norm_msb_e_in 13'0000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + assign \norm_msb_e_in \norm1_insel_z_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:107" + wire width 13 \ediff_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:110" + wire width 14 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:110" + wire width 14 $19 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:110" + cell $sub $20 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A 13'1110000000010 + connect \B \norm1_insel_z_z_e + connect \Y $19 + end + connect $18 $19 + process $group_26 + assign \ediff_n126 13'0000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \ediff_n126 $18 [12:0] + end + sync init + end + process $group_27 + assign \norm_exp_m_in 57'000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \norm_exp_m_in \temp_m + end + sync init + end + process $group_28 + assign \norm_exp_e_in 13'0000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \norm_exp_e_in \norm1_insel_z_z_e + end + sync init + end + process $group_29 + assign \norm_exp_ediff 13'0000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + switch { \increase \decrease } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:87" + case 2'-1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:106" + case 2'1- + assign \norm_exp_ediff \ediff_n126 + end + sync init + end + process $group_30 + assign \norm1_roundz 1'0 + assign \norm1_roundz \norm1_out_overflow_norm1of_roundz_out + sync init + end + process $group_31 + assign \muxid__6 2'00 + assign \muxid__6 \muxid + sync init + end + process $group_32 + assign \op__7 0'0 + assign \op__7 \op + sync init + end + process $group_33 + assign \out_do_z__4 1'0 + assign \out_do_z__4 \out_do_z + sync init + end + process $group_34 + assign \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__5 \oz + sync init + end + connect \op__7 0'0 + connect \op__13 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.roundz" +module \roundz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 0 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 1 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 2 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:25" + wire width 1 input 3 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:26" + wire width 64 input 4 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:23" + wire width 1 input 5 \norm1_roundz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 6 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 7 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 8 \z_s__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 9 \z_e__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 10 \z_m__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22" + wire width 1 output 11 \out_do_z__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23" + wire width 64 output 12 \oz__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 13 \muxid__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 14 \op__7 + process $group_0 + assign \z_s__1 1'0 + assign \z_s__1 \z_s + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52" + wire width 14 $8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52" + wire width 14 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52" + cell $add $10 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \z_e + connect \B 13'0000000000001 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 14 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + cell $pos $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \z_e + connect \Y $11 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:49" + wire width 1 \msb1s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52" + wire width 1 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52" + cell $and $15 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \msb1s + connect \B \norm1_roundz + connect \Y $14 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:52" + cell $mux $16 + parameter \WIDTH 4'1110 + connect \A $11 + connect \B $9 + connect \S $14 + connect \Y $13 + end + connect $8 $13 + process $group_1 + assign \z_e__2 13'0000000000000 + assign \z_e__2 \z_e + assign \z_e__2 $8 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51" + wire width 54 $17 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51" + wire width 54 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51" + cell $add $19 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 6'110110 + connect \A \z_m + connect \B 1'1 + connect \Y $18 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 54 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + cell $pos $21 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \Y_WIDTH 6'110110 + connect \A \z_m + connect \Y $20 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51" + wire width 54 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:51" + cell $mux $23 + parameter \WIDTH 6'110110 + connect \A $20 + connect \B $18 + connect \S \norm1_roundz + connect \Y $22 + end + connect $17 $22 + process $group_2 + assign \z_m__3 53'00000000000000000000000000000000000000000000000000000 + assign \z_m__3 \z_m + assign \z_m__3 $17 [52:0] + sync init + end + process $group_3 + assign \out_do_z__4 1'0 + assign \out_do_z__4 \out_do_z + sync init + end + process $group_4 + assign \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__5 \oz + sync init + end + process $group_5 + assign \muxid__6 2'00 + assign \muxid__6 \muxid + sync init + end + process $group_6 + assign \op__7 0'0 + assign \op__7 \op + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:50" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:50" + cell $reduce_and $25 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \z_m + connect \Y $24 + end + process $group_7 + assign \msb1s 1'0 + assign \msb1s $24 + sync init + end + connect \op__7 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.corrections.corr_in_z" +module \corr_in_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 0 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 1 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 output 2 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \z_e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \z_m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \z_m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.corrections" +module \corrections + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 0 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 1 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 2 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22" + wire width 1 input 3 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23" + wire width 64 input 4 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 5 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 6 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 output 7 \z_s__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 output 8 \z_e__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 output 9 \z_m__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22" + wire width 1 output 10 \out_do_z__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23" + wire width 64 output 11 \oz__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 12 \muxid__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 13 \op__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \corr_in_z_is_denormalised + cell \corr_in_z \corr_in_z + connect \z_e \z_e + connect \z_m \z_m + connect \is_denormalised \corr_in_z_is_denormalised + end + process $group_0 + assign \z_s__1 1'0 + assign \z_s__1 \z_s + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/corrections.py:30" + wire width 13 $8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/corrections.py:30" + cell $mux $9 + parameter \WIDTH 4'1101 + connect \A \z_e + connect \B 13'1110000000001 + connect \S \corr_in_z_is_denormalised + connect \Y $8 + end + process $group_1 + assign \z_e__2 13'0000000000000 + assign \z_e__2 \z_e + assign \z_e__2 $8 + sync init + end + process $group_2 + assign \z_m__3 53'00000000000000000000000000000000000000000000000000000 + assign \z_m__3 \z_m + sync init + end + process $group_3 + assign \out_do_z__4 1'0 + assign \out_do_z__4 \out_do_z + sync init + end + process $group_4 + assign \oz__5 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \oz__5 \oz + sync init + end + process $group_5 + assign \muxid__6 2'00 + assign \muxid__6 \muxid + sync init + end + process $group_6 + assign \op__7 0'0 + assign \op__7 \op + sync init + end + connect \op__7 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.pack.pack_in_z" +module \pack_in_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 0 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 1 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 output 2 \is_overflowed + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:471" + wire width 1 \is_nan + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:476" + wire width 1 \exp_128 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:484" + wire width 1 \m_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \m_zero + connect \Y $1 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:508" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B $1 + connect \Y $3 + end + process $group_0 + assign \is_nan 1'0 + assign \is_nan $3 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:472" + wire width 1 \is_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:482" + wire width 1 \exp_n127 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + wire width 1 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:514" + cell $and $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n127 + connect \B \m_zero + connect \Y $5 + end + process $group_1 + assign \is_zero 1'0 + assign \is_zero $5 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:473" + wire width 1 \is_inf + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + wire width 1 $7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:511" + cell $and $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_128 + connect \B \m_zero + connect \Y $7 + end + process $group_2 + assign \is_inf 1'0 + assign \is_inf $7 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:481" + wire width 1 \exp_gt127 + process $group_3 + assign \is_overflowed 1'0 + assign \is_overflowed \exp_gt127 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:475" + wire width 1 \is_denormalised + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:483" + wire width 1 \exp_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:485" + wire width 1 \m_msbzero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + wire width 1 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:522" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \exp_n126 + connect \B \m_msbzero + connect \Y $9 + end + process $group_4 + assign \is_denormalised 1'0 + assign \is_denormalised $9 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + wire width 1 $11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:494" + cell $eq $12 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0010000000000 + connect \Y $11 + end + process $group_5 + assign \exp_128 1'0 + assign \exp_128 $11 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:477" + wire width 13 \exp_sub_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + wire width 14 $14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:495" + cell $sub $15 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \z_e + connect \B 13'1110000000010 + connect \Y $14 + end + connect $13 $14 + process $group_6 + assign \exp_sub_n126 13'0000000000000 + assign \exp_sub_n126 $13 [12:0] + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:480" + wire width 1 \exp_gt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + wire width 1 $16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:496" + cell $gt $17 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $16 + end + process $group_7 + assign \exp_gt_n126 1'0 + assign \exp_gt_n126 $16 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:478" + wire width 1 \exp_lt_n126 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + wire width 1 $18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:497" + cell $lt $19 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \exp_sub_n126 + connect \B 13'0000000000000 + connect \Y $18 + end + process $group_8 + assign \exp_lt_n126 1'0 + assign \exp_lt_n126 $18 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:479" + wire width 1 \exp_zero + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + wire width 1 $20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:498" + cell $eq $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0000000000000 + connect \Y $20 + end + process $group_9 + assign \exp_zero 1'0 + assign \exp_zero $20 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:499" + cell $gt $23 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'0001111111111 + connect \Y $22 + end + process $group_10 + assign \exp_gt127 1'0 + assign \exp_gt127 $22 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:500" + cell $eq $25 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'1110000000001 + connect \Y $24 + end + process $group_11 + assign \exp_n127 1'0 + assign \exp_n127 $24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:501" + cell $eq $27 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 1'1 + connect \A \z_e + connect \B 13'1110000000010 + connect \Y $26 + end + process $group_12 + assign \exp_n126 1'0 + assign \exp_n126 $26 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:502" + cell $eq $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 6'110101 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 6'110101 + parameter \Y_WIDTH 1'1 + connect \A \z_m + connect \B 53'00000000000000000000000000000000000000000000000000000 + connect \Y $28 + end + process $group_13 + assign \m_zero 1'0 + assign \m_zero $28 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:503" + cell $eq $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \z_m [52] + connect \B 1'0 + connect \Y $30 + end + process $group_14 + assign \m_msbzero 1'0 + assign \m_msbzero $30 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack.pack" +module \pack + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 0 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 1 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 2 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22" + wire width 1 input 3 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23" + wire width 64 input 4 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 5 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 6 \op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 7 \z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 8 \muxid__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 9 \op__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:474" + wire width 1 \pack_in_z_is_overflowed + cell \pack_in_z \pack_in_z + connect \z_e \z_e + connect \z_m \z_m + connect \is_overflowed \pack_in_z_is_overflowed + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:366" + wire width 64 \z_v + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:33" + wire width 1 $3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:33" + cell $not $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \out_do_z + connect \Y $3 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + cell $add $7 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A 13'0010000000000 + connect \B 13'0001111111111 + connect \Y $6 + end + connect $5 $6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + wire width 14 $9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:412" + cell $add $10 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 4'1101 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 4'1101 + parameter \Y_WIDTH 4'1110 + connect \A \z_e + connect \B 13'0001111111111 + connect \Y $9 + end + connect $8 $9 + process $group_0 + assign \z_v 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:33" + switch { $3 } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:33" + case 1'1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:34" + switch { \pack_in_z_is_overflowed } + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:34" + case 1'1 + assign \z_v [51:0] 52'0000000000000000000000000000000000000000000000000000 + assign \z_v [62:52] $5 [10:0] + assign \z_v [63] \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:36" + case + assign \z_v [51:0] \z_m [51:0] + assign \z_v [62:52] $8 [10:0] + assign \z_v [63] \z_s + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pack.py:38" + case + assign \z_v \oz + end + sync init + end + process $group_1 + assign \muxid__1 2'00 + assign \muxid__1 \muxid + sync init + end + process $group_2 + assign \op__2 0'0 + assign \op__2 \op + sync init + end + process $group_3 + assign \z 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z \z_v + sync init + end + connect \op__2 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu.normpack" +module \normpack + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 input 2 \z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 input 3 \z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 input 4 \z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 input 5 \out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 input 6 \oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 input 7 \guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 input 8 \round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 input 9 \sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 input 10 \m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 input 11 \fflags + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 12 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 13 \op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 14 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 15 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 16 \z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 \z$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 17 \muxid__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__1$next + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 18 \op__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__2$next + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 19 \rst + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 20 \clk + cell \p__7 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n__8 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \normalise_1_z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \normalise_1_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \normalise_1_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 \normalise_1_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 \normalise_1_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 \normalise_1_guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 \normalise_1_round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 \normalise_1_sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 \normalise_1_m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 \normalise_1_fflags + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \normalise_1_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \normalise_1_op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \normalise_1_z_s__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \normalise_1_z_e__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \normalise_1_z_m__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:25" + wire width 1 \normalise_1_out_do_z__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:26" + wire width 64 \normalise_1_oz__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postnormalise.py:23" + wire width 1 \normalise_1_norm1_roundz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \normalise_1_muxid__8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \normalise_1_op__9 + cell \normalise_1 \normalise_1 + connect \z_s \normalise_1_z_s + connect \z_e \normalise_1_z_e + connect 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\op__7 \roundz_op__16 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \corrections_z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \corrections_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \corrections_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22" + wire width 1 \corrections_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23" + wire width 64 \corrections_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \corrections_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \corrections_op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \corrections_z_s__17 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \corrections_z_e__18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \corrections_z_m__19 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22" + wire width 1 \corrections_out_do_z__20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23" + wire width 64 \corrections_oz__21 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \corrections_muxid__22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \corrections_op__23 + cell \corrections \corrections + connect \z_s \corrections_z_s + connect \z_e \corrections_z_e + connect \z_m \corrections_z_m + connect \out_do_z \corrections_out_do_z + connect \oz \corrections_oz + connect \muxid \corrections_muxid + connect \op \corrections_op + connect \z_s__1 \corrections_z_s__17 + connect \z_e__2 \corrections_z_e__18 + connect \z_m__3 \corrections_z_m__19 + connect \out_do_z__4 \corrections_out_do_z__20 + connect \oz__5 \corrections_oz__21 + connect \muxid__6 \corrections_muxid__22 + connect \op__7 \corrections_op__23 + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \pack_z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \pack_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \pack_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:22" + wire width 1 \pack_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/roundz.py:23" + wire width 64 \pack_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pack_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \pack_op + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 \pack_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \pack_muxid__24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \pack_op__25 + cell \pack \pack + connect \z_s \pack_z_s + connect \z_e \pack_z_e + connect \z_m \pack_z_m + connect \out_do_z \pack_out_do_z + connect \oz \pack_oz + connect \muxid \pack_muxid + connect \op \pack_op + connect \z \pack_z + connect \muxid__1 \pack_muxid__24 + connect \op__2 \pack_op__25 + end + process $group_0 + assign \normalise_1_z_s 1'0 + assign \normalise_1_z_s \z_s + sync init + end + process $group_1 + assign \normalise_1_z_e 13'0000000000000 + assign \normalise_1_z_e \z_e + sync init + end + process $group_2 + assign \normalise_1_z_m 53'00000000000000000000000000000000000000000000000000000 + assign \normalise_1_z_m \z_m + sync init + end + process $group_3 + assign \normalise_1_out_do_z 1'0 + assign \normalise_1_out_do_z \out_do_z + sync init + end + process $group_4 + assign \normalise_1_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \normalise_1_oz \oz + sync init + end + process $group_5 + assign \normalise_1_guard 1'0 + assign \normalise_1_guard \guard + sync init + end + process $group_6 + assign \normalise_1_round 1'0 + assign \normalise_1_round \round + sync init + end + process $group_7 + assign \normalise_1_sticky 1'0 + assign \normalise_1_sticky \sticky + sync init + end + process $group_8 + assign \normalise_1_m0 1'0 + assign \normalise_1_m0 \m0 + sync init + end + process $group_9 + assign \normalise_1_fflags 5'00000 + assign \normalise_1_fflags \fflags + sync init + end + process $group_10 + assign \normalise_1_muxid 2'00 + assign \normalise_1_muxid \muxid + sync init + end + process $group_11 + assign \normalise_1_op 0'0 + assign \normalise_1_op \op + sync init + end + process $group_12 + assign \roundz_z_s 1'0 + assign \roundz_z_s \normalise_1_z_s__3 + sync init + end + process $group_13 + assign \roundz_z_e 13'0000000000000 + assign \roundz_z_e \normalise_1_z_e__4 + sync init + end + process $group_14 + assign \roundz_z_m 53'00000000000000000000000000000000000000000000000000000 + assign \roundz_z_m \normalise_1_z_m__5 + sync init + end + process $group_15 + assign \roundz_out_do_z 1'0 + assign \roundz_out_do_z \normalise_1_out_do_z__6 + sync init + end + process $group_16 + assign \roundz_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \roundz_oz \normalise_1_oz__7 + sync init + end + process $group_17 + assign \roundz_norm1_roundz 1'0 + assign \roundz_norm1_roundz \normalise_1_norm1_roundz + sync init + end + process $group_18 + assign \roundz_muxid 2'00 + assign \roundz_muxid \normalise_1_muxid__8 + sync init + end + process $group_19 + assign \roundz_op 0'0 + assign \roundz_op \normalise_1_op__9 + sync init + end + process $group_20 + assign \corrections_z_s 1'0 + assign \corrections_z_s \roundz_z_s__10 + sync init + end + process $group_21 + assign \corrections_z_e 13'0000000000000 + assign \corrections_z_e \roundz_z_e__11 + sync init + end + process $group_22 + assign \corrections_z_m 53'00000000000000000000000000000000000000000000000000000 + assign \corrections_z_m \roundz_z_m__12 + sync init + end + process $group_23 + assign \corrections_out_do_z 1'0 + assign \corrections_out_do_z \roundz_out_do_z__13 + sync init + end + process $group_24 + assign \corrections_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \corrections_oz \roundz_oz__14 + sync init + end + process $group_25 + assign \corrections_muxid 2'00 + assign \corrections_muxid \roundz_muxid__15 + sync init + end + process $group_26 + assign \corrections_op 0'0 + assign \corrections_op \roundz_op__16 + sync init + end + process $group_27 + assign \pack_z_s 1'0 + assign \pack_z_s \corrections_z_s__17 + sync init + end + process $group_28 + assign \pack_z_e 13'0000000000000 + assign \pack_z_e \corrections_z_e__18 + sync init + end + process $group_29 + assign \pack_z_m 53'00000000000000000000000000000000000000000000000000000 + assign \pack_z_m \corrections_z_m__19 + sync init + end + process $group_30 + assign \pack_out_do_z 1'0 + assign \pack_out_do_z \corrections_out_do_z__20 + sync init + end + process $group_31 + assign \pack_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \pack_oz \corrections_oz__21 + sync init + end + process $group_32 + assign \pack_muxid 2'00 + assign \pack_muxid \corrections_muxid__22 + sync init + end + process $group_33 + assign \pack_op 0'0 + assign \pack_op \corrections_op__23 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:621" + wire width 1 \p_valid_i__26 + process $group_34 + assign \p_valid_i__26 1'0 + assign \p_valid_i__26 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:619" + wire width 1 \n_i_rdy_data + process $group_35 + assign \n_i_rdy_data 1'0 + assign \n_i_rdy_data \n_ready_i + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:620" + wire width 1 \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624" + wire width 1 $27 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:624" + cell $and $28 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__26 + connect \B \p_ready_o + connect \Y $27 + end + process $group_36 + assign \p_valid_i_p_ready_o 1'0 + assign \p_valid_i_p_ready_o $27 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 \z__29 + process $group_37 + assign \z__29 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z__29 \pack_z + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__30 + process $group_38 + assign \muxid__30 2'00 + assign \muxid__30 \pack_muxid__24 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__31 + process $group_39 + assign \op__31 0'0 + assign \op__31 \pack_op__25 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:615" + wire width 1 \r_busy$next + process $group_40 + assign \r_busy$next \r_busy + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \r_busy$next 1'1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \r_busy$next 1'0 + end + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/xfrm.py:528" + switch \rst + case 1'1 + assign \r_busy$next 1'0 + end + sync init + update \r_busy 1'0 + sync posedge \clk + update \r_busy \r_busy$next + end + process $group_41 + assign \z$next \z + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \z$next \z__29 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \z$next \z__29 + end + sync init + update \z 64'0000000000000000000000000000000000000000000000000000000000000000 + sync posedge \clk + update \z \z$next + end + process $group_42 + assign \muxid__1$next \muxid__1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \muxid__1$next \muxid__30 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \muxid__1$next \muxid__30 + end + sync init + update \muxid__1 2'00 + sync posedge \clk + update \muxid__1 \muxid__1$next + end + process $group_43 + assign \op__2$next \op__2 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:631" + case 2'-1 + assign \op__2$next \op__31 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/singlepipe.py:637" + case 2'1- + assign \op__2$next \op__31 + end + sync init + update \op__2 0'0 + sync posedge \clk + update \op__2 \op__2$next + end + process $group_44 + assign \n_valid_o 1'0 + assign \n_valid_o \r_busy + sync init + end + process $group_45 + assign \p_ready_o 1'0 + assign \p_ready_o \n_i_rdy_data + sync init + end + connect \op__2 0'0 + connect \normalise_1_op 0'0 + connect \roundz_op 0'0 + connect \corrections_op 0'0 + connect \pack_op 0'0 + connect \op__31 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.alu" +module \alu + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 2 \a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 3 \b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 4 \c + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 5 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 6 \op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 7 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 8 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 9 \z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 10 \muxid__1 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 11 \op__2 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 12 \rst + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 13 \clk + cell \p \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n__1 \n + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 \scnorm_n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 \scnorm_n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \scnorm_z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \scnorm_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \scnorm_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \scnorm_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \scnorm_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \scnorm_a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \scnorm_a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \scnorm_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \scnorm_b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \scnorm_b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \scnorm_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \scnorm_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \scnorm_op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 \scnorm_p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 \scnorm_p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \scnorm_a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \scnorm_b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \scnorm_c + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \scnorm_muxid__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \scnorm_op__4 + cell \scnorm \scnorm + connect \n_valid_o \scnorm_n_valid_o + connect \n_ready_i \scnorm_n_ready_i + connect \z_s \scnorm_z_s + connect \z_e \scnorm_z_e + connect \z_m \scnorm_z_m + connect \out_do_z \scnorm_out_do_z + connect \oz \scnorm_oz + connect \a_s \scnorm_a_s + connect \a_e \scnorm_a_e + connect \a_m \scnorm_a_m + connect \b_s \scnorm_b_s + connect \b_e \scnorm_b_e + connect \b_m \scnorm_b_m + connect \muxid \scnorm_muxid + connect \op \scnorm_op + connect \p_valid_i \scnorm_p_valid_i + connect \p_ready_o \scnorm_p_ready_o + connect \a \scnorm_a + connect \b \scnorm_b + connect \c \scnorm_c + connect \muxid__1 \scnorm_muxid__3 + connect \op__2 \scnorm_op__4 + connect \rst \rst + connect \clk \clk + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 \mulstages_p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 \mulstages_p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mulstages_z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mulstages_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \mulstages_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:24" + wire width 1 \mulstages_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/pscdata.py:23" + wire width 64 \mulstages_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mulstages_a_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mulstages_a_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \mulstages_a_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mulstages_b_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mulstages_b_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \mulstages_b_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \mulstages_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \mulstages_op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 \mulstages_n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 \mulstages_n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \mulstages_z_s__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \mulstages_z_e__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \mulstages_z_m__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 \mulstages_out_do_z__8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 \mulstages_oz__9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 \mulstages_guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 \mulstages_round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 \mulstages_sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 \mulstages_m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 \mulstages_fflags + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \mulstages_muxid__10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \mulstages_op__11 + cell \mulstages \mulstages + connect \p_valid_i \mulstages_p_valid_i + connect \p_ready_o \mulstages_p_ready_o + connect \z_s \mulstages_z_s + connect \z_e \mulstages_z_e + connect \z_m \mulstages_z_m + connect \out_do_z \mulstages_out_do_z + connect \oz \mulstages_oz + connect \a_s \mulstages_a_s + connect \a_e \mulstages_a_e + connect \a_m \mulstages_a_m + connect \b_s \mulstages_b_s + connect \b_e \mulstages_b_e + connect \b_m \mulstages_b_m + connect \muxid \mulstages_muxid + connect \op \mulstages_op + connect \n_valid_o \mulstages_n_valid_o + connect \n_ready_i \mulstages_n_ready_i + connect \z_s__1 \mulstages_z_s__5 + connect \z_e__2 \mulstages_z_e__6 + connect \z_m__3 \mulstages_z_m__7 + connect \out_do_z__4 \mulstages_out_do_z__8 + connect \oz__5 \mulstages_oz__9 + connect \guard \mulstages_guard + connect \round \mulstages_round + connect \sticky \mulstages_sticky + connect \m0 \mulstages_m0 + connect \fflags \mulstages_fflags + connect \muxid__6 \mulstages_muxid__10 + connect \op__7 \mulstages_op__11 + connect \rst \rst + connect \clk \clk + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 \normpack_p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 \normpack_p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:370" + wire width 1 \normpack_z_s + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:369" + wire width 13 \normpack_z_e + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:367" + wire width 53 \normpack_z_m + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:15" + wire width 1 \normpack_out_do_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/postcalc.py:16" + wire width 64 \normpack_oz + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:889" + wire width 1 \normpack_guard + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:890" + wire width 1 \normpack_round + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:891" + wire width 1 \normpack_sticky + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:892" + wire width 1 \normpack_m0 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/fpbase.py:893" + wire width 5 \normpack_fflags + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \normpack_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \normpack_op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 \normpack_n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 \normpack_n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 \normpack_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \normpack_muxid__12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \normpack_op__13 + cell \normpack \normpack + connect \p_valid_i \normpack_p_valid_i + connect \p_ready_o \normpack_p_ready_o + connect \z_s \normpack_z_s + connect \z_e \normpack_z_e + connect \z_m \normpack_z_m + connect \out_do_z \normpack_out_do_z + connect \oz \normpack_oz + connect \guard \normpack_guard + connect \round \normpack_round + connect \sticky \normpack_sticky + connect \m0 \normpack_m0 + connect \fflags \normpack_fflags + connect \muxid \normpack_muxid + connect \op \normpack_op + connect \n_valid_o \normpack_n_valid_o + connect \n_ready_i \normpack_n_ready_i + connect \z \normpack_z + connect \muxid__1 \normpack_muxid__12 + connect \op__2 \normpack_op__13 + connect \rst \rst + connect \clk \clk + end + process $group_0 + assign \mulstages_p_valid_i 1'0 + assign \mulstages_p_valid_i \scnorm_n_valid_o + sync init + end + process $group_1 + assign \scnorm_n_ready_i 1'0 + assign \scnorm_n_ready_i \mulstages_p_ready_o + sync init + end + process $group_2 + assign \mulstages_z_s 1'0 + assign \mulstages_z_s \scnorm_z_s + sync init + end + process $group_3 + assign \mulstages_z_e 13'0000000000000 + assign \mulstages_z_e \scnorm_z_e + sync init + end + process $group_4 + assign \mulstages_z_m 53'00000000000000000000000000000000000000000000000000000 + assign \mulstages_z_m \scnorm_z_m + sync init + end + process $group_5 + assign \mulstages_out_do_z 1'0 + assign \mulstages_out_do_z \scnorm_out_do_z + sync init + end + process $group_6 + assign \mulstages_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \mulstages_oz \scnorm_oz + sync init + end + process $group_7 + assign \mulstages_a_s 1'0 + assign \mulstages_a_s \scnorm_a_s + sync init + end + process $group_8 + assign \mulstages_a_e 13'0000000000000 + assign \mulstages_a_e \scnorm_a_e + sync init + end + process $group_9 + assign \mulstages_a_m 53'00000000000000000000000000000000000000000000000000000 + assign \mulstages_a_m \scnorm_a_m + sync init + end + process $group_10 + assign \mulstages_b_s 1'0 + assign \mulstages_b_s \scnorm_b_s + sync init + end + process $group_11 + assign \mulstages_b_e 13'0000000000000 + assign \mulstages_b_e \scnorm_b_e + sync init + end + process $group_12 + assign \mulstages_b_m 53'00000000000000000000000000000000000000000000000000000 + assign \mulstages_b_m \scnorm_b_m + sync init + end + process $group_13 + assign \mulstages_muxid 2'00 + assign \mulstages_muxid \scnorm_muxid + sync init + end + process $group_14 + assign \mulstages_op 0'0 + assign \mulstages_op \scnorm_op + sync init + end + process $group_15 + assign \normpack_p_valid_i 1'0 + assign \normpack_p_valid_i \mulstages_n_valid_o + sync init + end + process $group_16 + assign \mulstages_n_ready_i 1'0 + assign \mulstages_n_ready_i \normpack_p_ready_o + sync init + end + process $group_17 + assign \normpack_z_s 1'0 + assign \normpack_z_s \mulstages_z_s__5 + sync init + end + process $group_18 + assign \normpack_z_e 13'0000000000000 + assign \normpack_z_e \mulstages_z_e__6 + sync init + end + process $group_19 + assign \normpack_z_m 53'00000000000000000000000000000000000000000000000000000 + assign \normpack_z_m \mulstages_z_m__7 + sync init + end + process $group_20 + assign \normpack_out_do_z 1'0 + assign \normpack_out_do_z \mulstages_out_do_z__8 + sync init + end + process $group_21 + assign \normpack_oz 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \normpack_oz \mulstages_oz__9 + sync init + end + process $group_22 + assign \normpack_guard 1'0 + assign \normpack_guard \mulstages_guard + sync init + end + process $group_23 + assign \normpack_round 1'0 + assign \normpack_round \mulstages_round + sync init + end + process $group_24 + assign \normpack_sticky 1'0 + assign \normpack_sticky \mulstages_sticky + sync init + end + process $group_25 + assign \normpack_m0 1'0 + assign \normpack_m0 \mulstages_m0 + sync init + end + process $group_26 + assign \normpack_fflags 5'00000 + assign \normpack_fflags \mulstages_fflags + sync init + end + process $group_27 + assign \normpack_muxid 2'00 + assign \normpack_muxid \mulstages_muxid__10 + sync init + end + process $group_28 + assign \normpack_op 0'0 + assign \normpack_op \mulstages_op__11 + sync init + end + process $group_29 + assign \scnorm_p_valid_i 1'0 + assign \scnorm_p_valid_i \p_valid_i + sync init + end + process $group_30 + assign \p_ready_o 1'0 + assign \p_ready_o \scnorm_p_ready_o + sync init + end + process $group_31 + assign \scnorm_a 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \scnorm_a \a + sync init + end + process $group_32 + assign \scnorm_b 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \scnorm_b \b + sync init + end + process $group_33 + assign \scnorm_c 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \scnorm_c \c + sync init + end + process $group_34 + assign \scnorm_muxid__3 2'00 + assign \scnorm_muxid__3 \muxid + sync init + end + process $group_35 + assign \scnorm_op__4 0'0 + assign \scnorm_op__4 \op + sync init + end + process $group_36 + assign \n_valid_o 1'0 + assign \n_valid_o \normpack_n_valid_o + sync init + end + process $group_37 + assign \normpack_n_ready_i 1'0 + assign \normpack_n_ready_i \n_ready_i + sync init + end + process $group_38 + assign \z 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z \normpack_z + sync init + end + process $group_39 + assign \muxid__1 2'00 + assign \muxid__1 \normpack_muxid__12 + sync init + end + process $group_40 + assign \op__2 0'0 + assign \op__2 \normpack_op__13 + sync init + end + connect \op__2 0'0 + connect \scnorm_op__4 0'0 + connect \mulstages_op 0'0 + connect \normpack_op 0'0 +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.outpipe.p" +module \p__10 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 input 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:126" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:173" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.outpipe.n0" +module \n0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.outpipe.n1" +module \n1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.outpipe.n2" +module \n2 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.outpipe.n3" +module \n3 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 input 0 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 1 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:218" + wire width 1 \trigger + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + wire width 1 $1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:264" + cell $and $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $1 + end + process $group_0 + assign \trigger 1'0 + assign \trigger $1 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.outpipe" +module \outpipe + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 input 2 \z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 3 \m_id + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 4 \op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 5 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 6 \n_valid_o__1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 7 \n_valid_o__2 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 8 \n_valid_o__3 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 9 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 10 \n_ready_i__4 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 11 \n_ready_i__5 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 12 \n_ready_i__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 13 \z__7 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 14 \z__8 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 15 \z__9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 16 \z__10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 17 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 18 \muxid__11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 19 \muxid__12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 20 \muxid__13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 21 \op__14 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 22 \op__15 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 23 \op__16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 24 \op__17 + cell \p__10 \p + connect \p_valid_i \p_valid_i + connect \p_ready_o \p_ready_o + end + cell \n0 \n0 + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + end + cell \n1 \n1 + connect \n_valid_o \n_valid_o__1 + connect \n_ready_i \n_ready_i__4 + end + cell \n2 \n2 + connect \n_valid_o \n_valid_o__2 + connect \n_ready_i \n_ready_i__5 + end + cell \n3 \n3 + connect \n_valid_o \n_valid_o__3 + connect \n_ready_i \n_ready_i__6 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:210" + wire width 1 \p_valid_i__18 + process $group_0 + assign \p_valid_i__18 1'0 + assign \p_valid_i__18 \p_valid_i + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:211" + wire width 1 \pv + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:214" + wire width 1 $19 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:214" + cell $and $20 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $19 + end + process $group_1 + assign \pv 1'0 + assign \pv $19 + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $21 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $22 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $not $23 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i + connect \Y $22 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $24 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $and $25 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $22 + connect \B \n_valid_o + connect \Y $24 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $26 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $or $27 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__18 + connect \B $24 + connect \Y $26 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $28 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $not $29 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i__4 + connect \Y $28 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $30 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $and $31 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $28 + connect \B \n_valid_o__1 + connect \Y $30 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $32 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $or $33 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__18 + connect \B $30 + connect \Y $32 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $34 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $not $35 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i__5 + connect \Y $34 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $36 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $and $37 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $34 + connect \B \n_valid_o__2 + connect \Y $36 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $38 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $or $39 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__18 + connect \B $36 + connect \Y $38 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $40 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $not $41 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_ready_i__6 + connect \Y $40 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $42 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $and $43 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $40 + connect \B \n_valid_o__3 + connect \Y $42 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + wire width 1 $44 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + cell $or $45 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \p_valid_i__18 + connect \B $42 + connect \Y $44 + end + process $group_2 + assign \n_valid_o 1'0 + assign \n_valid_o__1 1'0 + assign \n_valid_o__2 1'0 + assign \n_valid_o__3 1'0 + assign \n_valid_o 1'0 + assign \n_valid_o__1 1'0 + assign \n_valid_o__2 1'0 + assign \n_valid_o__3 1'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:228" + switch \m_id + case 2'00 + assign \n_valid_o $26 + case 2'01 + assign \n_valid_o__1 $32 + case 2'10 + assign \n_valid_o__2 $38 + case 2'-- + assign \n_valid_o__3 $44 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $46 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $47 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + cell $not $48 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_valid_o + connect \Y $47 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $49 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + cell $or $50 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $47 + connect \B \n_ready_i + connect \Y $49 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $51 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + cell $not $52 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_valid_o__1 + connect \Y $51 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $53 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + cell $or $54 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $51 + connect \B \n_ready_i__4 + connect \Y $53 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $55 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + cell $not $56 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_valid_o__2 + connect \Y $55 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $57 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + cell $or $58 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $55 + connect \B \n_ready_i__5 + connect \Y $57 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $59 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + cell $not $60 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A \n_valid_o__3 + connect \Y $59 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + wire width 1 $61 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:226" + cell $or $62 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $59 + connect \B \n_ready_i__6 + connect \Y $61 + end + process $group_6 + assign \p_ready_o 1'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/multipipe.py:225" + switch \m_id + case 2'00 + assign \p_ready_o $49 + case 2'01 + assign \p_ready_o $53 + case 2'10 + assign \p_ready_o $57 + case 2'-- + assign \p_ready_o $61 + end + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 \z__63 + process $group_7 + assign \z__63 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z__63 \z + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \muxid__64 + process $group_8 + assign \muxid__64 2'00 + assign \muxid__64 \m_id + sync init + end + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \op__65 + process $group_9 + assign \op__65 0'0 + assign \op__65 \op + sync init + end + process $group_10 + assign \z__7 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z__8 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z__9 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z__10 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/nmoperator.py:99" + switch \m_id + case 2'00 + assign \z__7 \z__63 + case 2'01 + assign \z__8 \z__63 + case 2'10 + assign \z__9 \z__63 + case 2'-- + assign \z__10 \z__63 + end + sync init + end + process $group_14 + assign \muxid 2'00 + assign \muxid__11 2'00 + assign \muxid__12 2'00 + assign \muxid__13 2'00 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/nmoperator.py:99" + switch \m_id + case 2'00 + assign \muxid \muxid__64 + case 2'01 + assign \muxid__11 \muxid__64 + case 2'10 + assign \muxid__12 \muxid__64 + case 2'-- + assign \muxid__13 \muxid__64 + end + sync init + end + process $group_18 + assign \op__14 0'0 + assign \op__15 0'0 + assign \op__16 0'0 + assign \op__17 0'0 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/nmoperator.py:99" + switch \m_id + case 2'00 + assign \op__14 \op__65 + case 2'01 + assign \op__15 \op__65 + case 2'10 + assign \op__16 \op__65 + case 2'-- + assign \op__17 \op__65 + end + sync init + end + connect \op__14 0'0 + connect \op__15 0'0 + connect \op__16 0'0 + connect \op__17 0'0 + connect \op__65 0'0 +end +attribute \generator "nMigen" +attribute \top 1 +attribute \nmigen.hierarchy "top" +module \fpmul64 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 0 \p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 1 \p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 2 \a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 3 \b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 4 \c + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 5 \muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 6 \op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 7 \p_valid_i__1 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 8 \p_ready_o__2 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 9 \a__3 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 10 \b__4 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 11 \c__5 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 12 \muxid__6 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 13 \op__7 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 14 \p_valid_i__8 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 15 \p_ready_o__9 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 16 \a__10 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 17 \b__11 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 18 \c__12 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 19 \muxid__13 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 20 \op__14 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 input 21 \p_valid_i__15 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 22 \p_ready_o__16 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 23 \a__17 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 24 \b__18 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 input 25 \c__19 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 input 26 \muxid__20 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 input 27 \op__21 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 output 28 \n_ready_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 29 \n_valid_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 output 30 \a__22 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 output 31 \b__23 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 output 32 \c__24 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 33 \muxid__25 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 34 \op__26 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 output 35 \p_valid_i__27 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 output 36 \p_ready_o__28 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 37 \z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 38 \m_id + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 39 \op__29 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 40 \n_ready_i__30 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 41 \n_valid_o__31 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 42 \z__32 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 43 \muxid__33 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 44 \op__34 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 45 \n_ready_i__35 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 46 \n_valid_o__36 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 47 \z__37 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 48 \muxid__38 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 49 \op__39 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 50 \n_ready_i__40 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 51 \n_valid_o__41 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 52 \z__42 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 53 \muxid__43 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 54 \op__44 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 input 55 \n_ready_i__45 + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 output 56 \n_valid_o__46 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 output 57 \z__47 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 output 58 \muxid__48 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 output 59 \op__49 + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 60 \clk + attribute \src "/home/lkcl/src/libreriscv/nmigen/nmigen/hdl/ir.py:540" + wire width 1 input 61 \rst + cell \inpipe \inpipe + connect \n_valid_o \n_valid_o + connect \n_ready_i \n_ready_i + connect \a \a__22 + connect \b \b__23 + connect \c \c__24 + connect \muxid \muxid__25 + connect \op \op__26 + connect \p_ready_o \p_ready_o + connect \p_ready_o__1 \p_ready_o__2 + connect \p_ready_o__2 \p_ready_o__9 + connect \p_ready_o__3 \p_ready_o__16 + connect \p_valid_i \p_valid_i + connect \a__4 \a + connect \b__5 \b + connect \c__6 \c + connect \muxid__7 \muxid + connect \op__8 \op + connect \p_valid_i__9 \p_valid_i__1 + connect \a__10 \a__3 + connect \b__11 \b__4 + connect \c__12 \c__5 + connect \muxid__13 \muxid__6 + connect \op__14 \op__7 + connect \p_valid_i__15 \p_valid_i__8 + connect \a__16 \a__10 + connect \b__17 \b__11 + connect \c__18 \c__12 + connect \muxid__19 \muxid__13 + connect \op__20 \op__14 + connect \p_valid_i__21 \p_valid_i__15 + connect \a__22 \a__17 + connect \b__23 \b__18 + connect \c__24 \c__19 + connect \muxid__25 \muxid__20 + connect \op__26 \op__21 + end + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:121" + wire width 1 \alu_p_valid_i + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:122" + wire width 1 \alu_p_ready_o + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \alu_a + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \alu_b + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/basedata.py:17" + wire width 64 \alu_c + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \alu_muxid + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \alu_op + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:213" + wire width 1 \alu_n_valid_o + attribute \src "/home/lkcl/src/libreriscv/nmutil/src/nmutil/iocontrol.py:214" + wire width 1 \alu_n_ready_i + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/packdata.py:13" + wire width 64 \alu_z + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:60" + wire width 2 \alu_muxid__50 + attribute \src "/home/lkcl/src/libreriscv/ieee754fpu/src/ieee754/fpcommon/getop.py:63" + wire width 0 \alu_op__51 + cell \alu \alu + connect \p_valid_i \alu_p_valid_i + connect \p_ready_o \alu_p_ready_o + connect \a \alu_a + connect \b \alu_b + connect \c \alu_c + connect \muxid \alu_muxid + connect \op \alu_op + connect \n_valid_o \alu_n_valid_o + connect \n_ready_i \alu_n_ready_i + connect \z \alu_z + connect \muxid__1 \alu_muxid__50 + connect \op__2 \alu_op__51 + connect \rst \rst + connect \clk \clk + end + cell \outpipe \outpipe + connect \p_valid_i \p_valid_i__27 + connect \p_ready_o \p_ready_o__28 + connect \z \z + connect \m_id \m_id + connect \op \op__29 + connect \n_valid_o \n_valid_o__31 + connect \n_valid_o__1 \n_valid_o__36 + connect \n_valid_o__2 \n_valid_o__41 + connect \n_valid_o__3 \n_valid_o__46 + connect \n_ready_i \n_ready_i__30 + connect \n_ready_i__4 \n_ready_i__35 + connect \n_ready_i__5 \n_ready_i__40 + connect \n_ready_i__6 \n_ready_i__45 + connect \z__7 \z__32 + connect \z__8 \z__37 + connect \z__9 \z__42 + connect \z__10 \z__47 + connect \muxid \muxid__33 + connect \muxid__11 \muxid__38 + connect \muxid__12 \muxid__43 + connect \muxid__13 \muxid__48 + connect \op__14 \op__34 + connect \op__15 \op__39 + connect \op__16 \op__44 + connect \op__17 \op__49 + end + process $group_0 + assign \alu_p_valid_i 1'0 + assign \alu_p_valid_i \n_valid_o + sync init + end + process $group_1 + assign \n_ready_i 1'0 + assign \n_ready_i \alu_p_ready_o + sync init + end + process $group_2 + assign \alu_a 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_a \a__22 + sync init + end + process $group_3 + assign \alu_b 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_b \b__23 + sync init + end + process $group_4 + assign \alu_c 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \alu_c \c__24 + sync init + end + process $group_5 + assign \alu_muxid 2'00 + assign \alu_muxid \muxid__25 + sync init + end + process $group_6 + assign \alu_op 0'0 + assign \alu_op \op__26 + sync init + end + process $group_7 + assign \p_valid_i__27 1'0 + assign \p_valid_i__27 \alu_n_valid_o + sync init + end + process $group_8 + assign \alu_n_ready_i 1'0 + assign \alu_n_ready_i \p_ready_o__28 + sync init + end + process $group_9 + assign \z 64'0000000000000000000000000000000000000000000000000000000000000000 + assign \z \alu_z + sync init + end + process $group_10 + assign \m_id 2'00 + assign \m_id \alu_muxid__50 + sync init + end + process $group_11 + assign \op__29 0'0 + assign \op__29 \alu_op__51 + sync init + end + connect \op__29 0'0 + connect \alu_op 0'0 +end diff --git a/experiments6/mksym.sh b/experiments6/mksym.sh new file mode 100755 index 0000000..cea54b0 --- /dev/null +++ b/experiments6/mksym.sh @@ -0,0 +1,42 @@ +#!/bin/bash + +ALLIANCE_TOOLKIT=${ALLIANCE_TOOLKIT:-${HOME}/alliance-check-toolkit/} + +echo "creating symlinks" + +mkdir -p mk/dks.d +mkdir -p mk/users.d + +declare -a ScriptsArray=("os" "users" "binaries" "alliance" + "design-flow" "pr-coriolis" "pr-alliance" "pr-hibikino" + "synthesis-yosys" +) + +for script in "${ScriptsArray[@]}"; do + if [ ! -L "mk/$script.mk" ]; then + echo "link" mk/$script.mk + ln -s $ALLIANCE_TOOLKIT/etc/mk/$script.mk mk/$script.mk + fi +done + +declare -a LibsArray=("sxlib" "nsxlib" "nsxlib45" "cmos" +) + +for script in "${LibsArray[@]}"; do + if [ ! -L "mk/dks.d/$script.mk" ]; then + echo "link" mk/dks.d/$script.mk + ln -s $ALLIANCE_TOOLKIT/etc/mk/dks.d/$script.mk mk/dks.d/$script.mk + fi +done + +declare -a UsersArray=("lkcl" +) + +for script in "${UsersArray[@]}"; do + if [ ! -L "mk/users.d/user-$script.mk" ]; then + echo "link" mk/users.d/user-$script.mk + ln -s $ALLIANCE_TOOLKIT/etc/mk/users.d/user-$script.mk \ + mk/users.d/user-$script.mk + fi +done + diff --git a/experiments6/nets2.txt b/experiments6/nets2.txt new file mode 100644 index 0000000..e1c7931 --- /dev/null +++ b/experiments6/nets2.txt @@ -0,0 +1,54 @@ +fpmul64 +p0 +p1 +p2 +p3 +n +selector +p_mux +inpipe +p +n__1 +p__2 +n__3 +sc_decode_a +sc_decode_b +specialcases +denorm_in_a +denorm_in_b +denormalise +norm1_insel_a +norm1_insel_b +pe +norm_pe_a +pe__4 +norm_pe_b +align +scnorm +p__5 +n__6 +mul0 +mul1 +mulstages +p__7 +n__8 +norm1_out_overflow +norm1_insel_z +multishift_r +norm_exp +pe__9 +norm_msb +normalise_1 +roundz +corr_in_z +corrections +pack_in_z +pack +normpack +alu +p__10 +n0 +n1 +n2 +n3 +outpipe