From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 6 Jan 2020 19:53:48 +0000 (-0800)
Subject: Fixes
X-Git-Tag: working-ls180~881^2^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64ace4b0dc5c8dd24132bc8046b2bacc163f9164;p=yosys.git

Fixes
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3c781ca44..f82511407 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -411,6 +411,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 		if (mapped_mod == NULL)
 			log_error("ABC output file does not contain a module `$__abc9__'.\n");
 
+		for (auto w : mapped_mod->wires())
+			module->addWire(remap_name(w->name), GetSize(w));
+
 		dict<IdString, bool> abc9_box;
 		vector<RTLIL::Cell*> boxes;
 		for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {