From: Tobias Platen <tplaten@posteo.de>
Date: Sat, 2 Oct 2021 14:00:50 +0000 (+0200)
Subject: dcbz: cleanup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64b7674b21afd0654d447aed6d2bf26f19f5bf7a;p=soc.git

dcbz: cleanup
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 822fe109..376aeb64 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -522,6 +522,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # connect to LD/ST PortInterface.
         comb += pi.is_ld_i.eq(op_is_ld & busy_o)  # decoded-LD
         comb += pi.is_st_i.eq(op_is_st & busy_o)  # decoded-ST
+        comb += pi.is_dcbz_i.eq(op_is_dcbz & busy_o)  # decoded-DCBZ
         comb += pi.data_len.eq(oper_r.data_len)  # data_len
         # address: use sync to avoid long latency
         sync += pi.addr.data.eq(addr_r)           # EA from adder
diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index c561357a..89a5187f 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -100,7 +100,6 @@ class PortInterface(RecordObject):
         self.is_ld_i    = Signal(reset_less=True)
         self.is_st_i    = Signal(reset_less=True)
         self.is_dcbz_i  = Signal(reset_less=True)
-        ## self.is_dcbz = self.is_dcbz_i # renamed signal hack
 
         # LD/ST data length (TODO: other things may be needed)
         self.data_len = Signal(4, reset_less=True)
@@ -239,7 +238,7 @@ class PortInterfaceBase(Elaboratable):
         # activate mode: only on "edge"
         comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
         comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
-        comb += dcbz_active.s.eq(rising_edge(m, dcbzs))  # activate ST mode
+        comb += dcbz_active.s.eq(rising_edge(m, dcbzs))  # activate DCBZ mode
 
         # LD/ST requested activates "busy" (only if not already busy)
         with m.If(self.pi.is_ld_i | self.pi.is_st_i):
@@ -260,6 +259,7 @@ class PortInterfaceBase(Elaboratable):
         # if now in "DCBZ" mode: wait for addr_ok, then send the address out
         # to memory, acknowledge address, and send out LD data
         with m.If(dcbz_active.q):
+            ##comb += Display("dcbz active")
             self.set_dcbz_addr(m, pi.addr.data)
 
         # if now in "ST" mode: likewise do the same but with "ST"
diff --git a/src/soc/experiment/test/test_compldst_multi_mmu.py b/src/soc/experiment/test/test_compldst_multi_mmu.py
index 5b54ad11..021851a4 100644
--- a/src/soc/experiment/test/test_compldst_multi_mmu.py
+++ b/src/soc/experiment/test/test_compldst_multi_mmu.py
@@ -110,7 +110,7 @@ class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
         from soc.experiment.l0_cache import TstL0CacheBuffer
         from soc.fu.ldst.pipe_data import LDSTPipeSpec
         regspec = LDSTPipeSpec.regspec
-        self.l0 = l0 = TstL0CacheBuffer(pspec)
+        self.l0 = l0 = TstL0CacheBuffer(pspec) #this is wrong, see setup_mmu
         self.mmu = MMU()
         pi = l0.l0.dports[0]
         LDSTCompUnit.__init__(self, pi, regspec, 4)