From: higuoxing <higuoxing@web>
Date: Fri, 6 Apr 2018 07:20:12 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5755
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64c31a1ca3035ff478782f3b1f857fb9b5097b79;p=libreriscv.git

---

diff --git a/shakti/m_class/pinmux.mdwn b/shakti/m_class/pinmux.mdwn
index 79261c51b..ff37f952f 100644
--- a/shakti/m_class/pinmux.mdwn
+++ b/shakti/m_class/pinmux.mdwn
@@ -70,7 +70,7 @@ Introductions:
 Hardware available:
 
 * lkcl: ZC706
-* xing: zynq-7020 and Xilinx XC7A100T-484
+* xing: zynq-7020 and Xilinx XC7A100T-484 [Xing's Mail](higuoxing@gmail.com)
 
 # Discussion and Links
 
@@ -85,6 +85,7 @@ Hardware available:
 * <https://github.com/xfguo/tbgen/blob/master/tbgen.py> auto-generated test module for verilog
 * <https://github.com/kdurant/verilog-testbench> described here <https://www.vim.org/scripts/script.php?script_id=4596>
 * <http://agilesoc.com/open-source-projects/svunit/> - SVunit - unit testing for verilog
+* [FPGA Overview](http://www.springer.com/cda/content/document/cda_downloaddocument/9781461435938-c2.pdf?SGWID=0-0-45-1333135-p174308376) Useful in writing GPIO related codes...
 
 # Pinouts Specification