From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Sep 2018 05:46:08 +0000 (+0100)
Subject: rename sv vlen to sv voffs, add csr and reg tables
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64c3336d36a5e04d06053b4a6f433ea0a84c295e;p=riscv-isa-sim.git

rename sv vlen to sv voffs, add csr and reg tables
---

diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc
index 8856aab..46a5321 100644
--- a/riscv/insn_template.cc
+++ b/riscv/insn_template.cc
@@ -12,8 +12,8 @@ reg_t rv32_NAME(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t npc = sext_xlen(pc + insn_length(OPCODE));
   insn_bits_t bits = s_insn.bits();
 #ifdef SPIKE_SIMPLEV
-  int vlen = 1;
-  sv_insn_t insn(bits, vlen);
+  int voffs = 0;
+  sv_insn_t insn(bits, voffs);
   #include "insns/NAME.h"
   trace_opcode(p, OPCODE, s_insn);
 #else
@@ -30,8 +30,8 @@ reg_t rv64_NAME(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t npc = sext_xlen(pc + insn_length(OPCODE));
   insn_bits_t bits = s_insn.bits();
 #ifdef SPIKE_SIMPLEV
-  int vlen = 1;
-  sv_insn_t insn(bits, vlen);
+  int voffs = 0;
+  sv_insn_t insn(bits, voffs);
   #include "insns/NAME.h"
   trace_opcode(p, OPCODE, s_insn);
 #else
diff --git a/riscv/sv.cc b/riscv/sv.cc
new file mode 100644
index 0000000..824541c
--- /dev/null
+++ b/riscv/sv.cc
@@ -0,0 +1,8 @@
+#include "sv.h"
+
+sv_reg_csr_entry sv_csrs[SV_CSR_SZ];
+sv_reg_entry sv_int_tb[NXPR];
+sv_reg_entry sv_fp_tb[NFPR];
+sv_pred_csr_entry sv_pred_csrs[SV_CSR_SZ];
+sv_pred_entry sv_pred_tb[NXPR];
+
diff --git a/riscv/sv.h b/riscv/sv.h
index 58e5724..7b98c92 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -16,6 +16,10 @@ typedef struct {
     unsigned int packed : 1; // Packed SIMD=1
 } sv_reg_csr_entry;
 
+#define SV_CSR_SZ 16
+
+extern sv_reg_csr_entry sv_csrs[SV_CSR_SZ];
+
 // this is the "unpacked" table, generated from the CAM above
 // there are 2 of them: one for FP, one for INT regs.
 // one sv_reg_entry is required per FP *and* per INT reg.
@@ -30,6 +34,11 @@ typedef struct {
     unsigned int active : 1; // enabled=1, disabled=0
 } sv_reg_entry;
 
+// 32 entries: it's the size of the register table that needs to double
+// (regidx=6 i.e. actual target register is indexed by 2^6)
+extern sv_reg_entry sv_int_tb[NXPR];
+extern sv_reg_entry sv_fp_tb[NFPR];
+
 typedef struct {
     unsigned int type  : 1; // 0=INT, 1=FP
     unsigned int regkey: 5; // 5 bits: 
@@ -39,6 +48,8 @@ typedef struct {
     unsigned int active: 1; // enabled=1, disabled=0
 } sv_pred_csr_entry;
 
+extern sv_pred_csr_entry sv_pred_csrs[SV_CSR_SZ];
+
 typedef struct {
     unsigned int regkey: 5; // 5 bits: 
     unsigned int zero  : 1; // zeroing=1, skipping=0
@@ -47,4 +58,7 @@ typedef struct {
     unsigned int active: 1; // enabled=1, disabled=0
 } sv_pred_entry;
 
+// 32 entries, only integer regs are predicates.
+extern sv_pred_entry sv_pred_tb[NXPR];
+
 #endif
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 73a2941..14dad03 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -9,13 +9,13 @@
 class sv_insn_t: public insn_t
 {
 public:
-  sv_insn_t(insn_bits_t bits, int& v) : insn_t(bits), vlen(v) {}
+  sv_insn_t(insn_bits_t bits, int& v) : insn_t(bits), voffs(v) {}
   uint64_t rd () { return remap(insn_t::rd()); }
   uint64_t rs1() { return remap(insn_t::rs1()); }
   uint64_t rs2() { return remap(insn_t::rs2()); }
   uint64_t rs3() { return remap(insn_t::rs3()); }
 private:
-  int &vlen;
+  int &voffs;
   // remaps the register through the lookup table.
   // will need to take the current loop index/offset somehow
   uint64_t remap(uint64_t reg) { return reg; } // TODO