From: Florent Kermarrec Date: Sun, 25 Jan 2015 15:23:40 +0000 (+0100) Subject: change CSR class names (do not expose XXYYCSR to user) X-Git-Tag: 24jan2021_ls180~2575^2~35 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64d18796e0f8015c448d47d7c63362b7c4a39f4c;p=litex.git change CSR class names (do not expose XXYYCSR to user) --- diff --git a/README b/README index 6fc5063f..c310196d 100644 --- a/README +++ b/README @@ -15,7 +15,7 @@ LiteScope is small footprint and configurable embedded logic analyzer that you can use in your FPGA and aims to provide a a free, portable and flexible alternatve to vendor's solutions! -LiteScope is part of LiteX libraries whose aims is to lower entry level of complex +LiteScope is part of LiteX libraries whose aims are to lower entry level of complex FPGA IP cores by providing simple, elegant and efficient implementations of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... diff --git a/litescope/core/port.py b/litescope/core/port.py index b19c8f2d..eb681edf 100644 --- a/litescope/core/port.py +++ b/litescope/core/port.py @@ -1,6 +1,6 @@ from litescope.common import * -class LiteScopeTerm(Module): +class LiteScopeTermUnit(Module): def __init__(self, dw): self.dw = dw self.sink = sink = Sink(data_layout(dw)) @@ -15,9 +15,9 @@ class LiteScopeTerm(Module): sink.ack.eq(source.ack) ] -class LiteScopeTermCSR(LiteScopeTerm, AutoCSR): +class LiteScopeTerm(LiteScopeTermUnit, AutoCSR): def __init__(self, dw): - LiteScopeTerm.__init__(self, dw) + LiteScopeTermUnit.__init__(self, dw) self._trig = CSRStorage(dw) self._mask = CSRStorage(dw) ### @@ -26,7 +26,7 @@ class LiteScopeTermCSR(LiteScopeTerm, AutoCSR): self.mask.eq(self._mask.storage) ] -class LiteScopeRangeDetector(Module): +class LiteScopeRangeDetectorUnit(Module): def __init__(self, dw): self.dw = dw self.sink = sink = Sink(data_layout(dw)) @@ -41,9 +41,9 @@ class LiteScopeRangeDetector(Module): sink.ack.eq(source.ack) ] -class LiteScopeRangeDetectorCSR(LiteScopeRangeDetector, AutoCSR): +class LiteScopeRangeDetector(LiteScopeRangeDetectorUnit, AutoCSR): def __init__(self, dw): - LiteScopeRangeDetector.__init__(self, dw) + LiteScopeRangeDetectorUnit.__init__(self, dw) self._low = CSRStorage(dw) self._high = CSRStorage(dw) ### @@ -52,7 +52,7 @@ class LiteScopeRangeDetectorCSR(LiteScopeRangeDetector, AutoCSR): self.high.eq(self._high.storage) ] -class LiteScopeEdgeDetector(Module): +class LiteScopeEdgeDetectorUnit(Module): def __init__(self, dw): self.dw = dw self.sink = sink = Sink(data_layout(dw)) @@ -80,9 +80,9 @@ class LiteScopeEdgeDetector(Module): source.hit.eq(rising | falling | both) ] -class LiteScopeEdgeDetectorCSR(LiteScopeEdgeDetector, AutoCSR): +class LiteScopeEdgeDetector(LiteScopeEdgeDetectorUnit, AutoCSR): def __init__(self, dw): - LiteScopeEdgeDetector.__init__(self, dw) + LiteScopeEdgeDetectorUnit.__init__(self, dw) self._rising = CSRStorage(dw) self._falling = CSRStorage(dw) self._both = CSRStorage(dw) diff --git a/litescope/core/storage.py b/litescope/core/storage.py index 095a12a8..4c8d60a6 100644 --- a/litescope/core/storage.py +++ b/litescope/core/storage.py @@ -1,6 +1,6 @@ from litescope.common import * -class LiteScopeRunLengthEncoder(Module): +class LiteScopeRunLengthEncoderUnit(Module): def __init__(self, dw, length=1024): self.dw = dw self.length = length @@ -46,12 +46,12 @@ class LiteScopeRunLengthEncoder(Module): ) ) -class LiteScopeRunLengthEncoderCSR(Module, AutoCSR): - def __init__(self, rle): - self.submodules += rle +class LiteScopeRunLengthEncoder(LiteScopeRunLengthEncoderUnit, AutoCSR): + def __init__(self, dw, length=1024): + LiteScopeRunLengthEncoderUnit.__init__(self, dw, length) self._enable = CSRStorage() ### - self.comb += rle.enable.eq(self_enable.storage) + self.comb += self.enable.eq(self_enable.storage) class LiteScopeRecorder(Module, AutoCSR): def __init__(self, dw, depth): diff --git a/litescope/core/trigger.py b/litescope/core/trigger.py index f1c16877..403e8248 100644 --- a/litescope/core/trigger.py +++ b/litescope/core/trigger.py @@ -1,6 +1,6 @@ from litescope.common import * -class LiteScopeSum(Module, AutoCSR): +class LiteScopeSumUnit(Module, AutoCSR): def __init__(self, ports): self.sinks = sinks = [Sink(hit_layout()) for i in range(ports)] self.source = source = Source(hit_layout()) @@ -35,9 +35,9 @@ class LiteScopeSum(Module, AutoCSR): for i, sink in enumerate(sinks): self.comb += sink.ack.eq(sink.stb & source.ack) -class LiteScopeSumCSR(Module, AutoCSR): +class LiteScopeSum(LiteScopeSumUnit, AutoCSR): def __init__(self, ports): - LiteScopeSum.__init__(self, ports) + LiteScopeSumUnit.__init__(self, ports) self._prog_we = CSR() self._prog_adr = CSRStorage(ports) self._prog_dat = CSRStorage() @@ -60,7 +60,7 @@ class LiteScopeTrigger(Module, AutoCSR): self.ports.append(port) def do_finalize(self): - self.submodules.sum = LiteScopeSumCSR(len(self.ports)) + self.submodules.sum = LiteScopeSum(len(self.ports)) ### for i, port in enumerate(self.ports): # Note: port's ack is not used and supposed to be always 1 diff --git a/litescope/frontend/la.py b/litescope/frontend/la.py index 8bdd7199..f3025fc7 100644 --- a/litescope/frontend/la.py +++ b/litescope/frontend/la.py @@ -27,8 +27,8 @@ class LiteScopeLA(Module, AutoCSR): # insert Buffer on sink (optional, can be used to improve timings) if self.input_buffer: self.submodules.buffer = Buffer(self.sink.description) - self.comb += Record.connect(self.sink, self.buffer.sink) - self.sink = self.buffer.source + self.comb += Record.connect(self.sink, self.buffer.d) + self.sink = self.buffer.q # clock domain crossing (optional, required when capture_clk is not sys_clk) # XXX : sys_clk must be faster than capture_clk, add Converter on data to remove this limitation diff --git a/targets/simple.py b/targets/simple.py index 6fa3dc99..009c95a8 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -11,7 +11,7 @@ from litescope.common import * from litescope.bridge.uart2wb import LiteScopeUART2WB from litescope.frontend.io import LiteScopeIO from litescope.frontend.la import LiteScopeLA -from litescope.core.port import LiteScopeTermCSR +from litescope.core.port import LiteScopeTerm class _CRG(Module): def __init__(self, clk_in): @@ -98,7 +98,7 @@ class LiteScopeSoC(GenSoC, AutoCSR): cnt1 ) self.submodules.la = LiteScopeLA(self.debug, 512) - self.la.trigger.add_port(LiteScopeTermCSR(self.la.dw)) + self.la.trigger.add_port(LiteScopeTerm(self.la.dw)) atexit.register(self.exit, platform) def exit(self, platform):