From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 21 Aug 2019 03:07:38 +0000 (-0700)
Subject: Oops
X-Git-Tag: working-ls180~1075^2^2~47
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64d62710de4f1db0d59d7fa04b3fb4d51c8dff2e;p=yosys.git

Oops
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 3a58f32fa..80211619b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -299,7 +299,7 @@ endmodule
 
 module RAM32X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-  (* abc_arrival=11530 *) output DPO, SPO,
+  (* abc_arrival=1153 *) output DPO, SPO,
   input  D,
   input  WCLK,
   input  WE,