From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 11 Nov 2014 15:15:28 +0000 (+0100)
Subject: clean up
X-Git-Tag: 24jan2021_ls180~2572^2~164
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=64ed34b35a1b8a1c8ac2c38bd5dc2b6cc6f1449e;p=litex.git

clean up
---

diff --git a/Makefile b/Makefile
index f21ec5cd..190bf115 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 MSCDIR = ../misoc
-CURDIR = ../k7sataphy
+CURDIR = ../sata_controller
 PYTHON = python3
 TOOLCHAIN = vivado
 PLATFORM = kc705
diff --git a/lib/sata/link/__init__.py b/lib/sata/link/__init__.py
index 972c99a8..65eb8cab 100644
--- a/lib/sata/link/__init__.py
+++ b/lib/sata/link/__init__.py
@@ -64,10 +64,10 @@ class SATALinkLayer(Module):
 
 		# graph
 		self.comb += [
-			If(fsm.ongoing("H2D_COPY" & (rx_det == 0),
+			If(fsm.ongoing("H2D_COPY") & (rx_det == 0),
 				descrambler.sink.stb.eq(phy.source.stb & (phy.charisk == 0)),
 				descrambler.sink.d.eq(phy.source.d),
-			)
+			),
 			Record.connect(descrambler.source, crc_checker.sink),
 			Record.connect(crc_checker.source, self.source)
 		]
@@ -107,7 +107,7 @@ class SATALinkLayer(Module):
 		)
 		fsm.act("H2D_WTRM",
 			tx_insert.eq(primitives["WTRM"]),
-			If(rx_det == primitives["R_OK"]),
+			If(rx_det == primitives["R_OK"],
 				NextState("IDLE")
 			).Elif(rx_det == primitives["R_ERR"],
 				NextState("IDLE")
@@ -133,7 +133,7 @@ class SATALinkLayer(Module):
 		)
 		fsm.act("D2H_WTRM",
 			tx_insert.eq(primitives["R_OK"]),
-			If(rx_det == primitives["SYNC"]),
+			If(rx_det == primitives["SYNC"],
 				NextState("IDLE")
 			)
 		)
diff --git a/lib/sata/link/test/scrambler_tb.py b/lib/sata/link/test/scrambler_tb.py
index 6c9521f4..8228ef56 100644
--- a/lib/sata/link/test/scrambler_tb.py
+++ b/lib/sata/link/test/scrambler_tb.py
@@ -8,7 +8,7 @@ from lib.sata.link.test.common import check
 
 class TB(Module):
 	def __init__(self, length):
-		self.submodules.scrambler = SATAScrambler()
+		self.submodules.scrambler = Scrambler()
 		self.length = length
 
 	def gen_simulation(self, selfp):
diff --git a/lib/sata/phy/k7sataphy/__init__.py b/lib/sata/phy/k7sataphy/__init__.py
index ba4ef1b4..d1c8c8ff 100644
--- a/lib/sata/phy/k7sataphy/__init__.py
+++ b/lib/sata/phy/k7sataphy/__init__.py
@@ -1,10 +1,10 @@
 from migen.fhdl.std import *
 
-from lib.sata.k7sataphy.std import *
-from lib.sata.k7sataphy.gtx import K7SATAPHYGTX
-from lib.sata.k7sataphy.crg import K7SATAPHYCRG
-from lib.sata.k7sataphy.ctrl import K7SATAPHYHostCtrl, K7SATAPHYDeviceCtrl
-from lib.sata.k7sataphy.datapath import K7SATAPHYDatapath
+from lib.sata.std import *
+from lib.sata.phy.k7sataphy.gtx import K7SATAPHYGTX
+from lib.sata.phy.k7sataphy.crg import K7SATAPHYCRG
+from lib.sata.phy.k7sataphy.ctrl import K7SATAPHYHostCtrl, K7SATAPHYDeviceCtrl
+from lib.sata.phy.k7sataphy.datapath import K7SATAPHYDatapath
 
 class K7SATAPHY(Module):
 	def __init__(self, pads, clk_freq, host=True, default_speed="SATA1"):
diff --git a/lib/sata/phy/k7sataphy/crg.py b/lib/sata/phy/k7sataphy/crg.py
index aae3a938..25a2f784 100644
--- a/lib/sata/phy/k7sataphy/crg.py
+++ b/lib/sata/phy/k7sataphy/crg.py
@@ -5,7 +5,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.fsm import FSM, NextState
 
 from lib.sata.std import *
-from lib.sata.k7sataphy.gtx import GTXE2_COMMON
+from lib.sata.phy.k7sataphy.gtx import GTXE2_COMMON
 
 class K7SATAPHYCRG(Module):
 	def __init__(self, pads, gtx, clk_freq, default_speed):
diff --git a/lib/sata/phy/k7sataphy/datapath.py b/lib/sata/phy/k7sataphy/datapath.py
index 922c1f32..809d4e8a 100644
--- a/lib/sata/phy/k7sataphy/datapath.py
+++ b/lib/sata/phy/k7sataphy/datapath.py
@@ -132,7 +132,7 @@ class K7SATAPHYDatapath(Module):
 		self.sync += \
 			If(~ctrl.ready,
 				align_cnt.eq(0)
-			).Elsif(tx.sink.stb & tx.sink.ack,
+			).Elif(tx.sink.stb & tx.sink.ack,
 				align_cnt.eq(align_cnt+1)
 			)
 		send_align = (align_cnt < 2)
@@ -151,8 +151,7 @@ class K7SATAPHYDatapath(Module):
 					tx.sink.data.eq(self.sink.data),
 					tx.sink.charisk.eq(self.sink.charisk),
 					self.sink.ack.eq(tx.sink.ack)
-				)
-
+				),
 				self.source.stb.eq(rx.source.stb),
 				self.source.data.eq(rx.source.data),
 				self.source.charisk.eq(rx.source.charisk),
diff --git a/targets/test.py b/targets/test.py
index 1cb99610..53a55822 100644
--- a/targets/test.py
+++ b/targets/test.py
@@ -8,7 +8,7 @@ from migen.bank.description import *
 from miscope.uart2wishbone import UART2Wishbone
 
 from misoclib import identifier
-from lib.sata.phy.k7sataphy.std import *
+from lib.sata.std import *
 from lib.sata.phy.k7sataphy import K7SATAPHY
 
 from migen.genlib.cdc import *
@@ -101,13 +101,13 @@ class SimDesign(UART2WB):
 		self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True)
 		self.comb += [
 			self.sataphy_host.sink.stb.eq(1),
-			self.sataphy_host.sink.data.eq(SYNC_VAL),
+			self.sataphy_host.sink.data.eq(primitives["SYNC"]),
 			self.sataphy_host.sink.charisk.eq(0b0001)
 		]
 		self.submodules.sataphy_device = K7SATAPHY(platform.request("sata_device"), clk_freq, host=False)
 		self.comb += [
 			self.sataphy_device.sink.stb.eq(1),
-			self.sataphy_device.sink.data.eq(SYNC_VAL),
+			self.sataphy_device.sink.data.eq(primitives["SYNC"]),
 			self.sataphy_device.sink.charisk.eq(0b0001)
 		]
 
@@ -151,7 +151,7 @@ class TestDesign(UART2WB, AutoCSR):
 		self.submodules.sataphy_host = K7SATAPHY(platform.request("sata_host"), clk_freq, host=True, default_speed="SATA2")
 		self.comb += [
 			self.sataphy_host.sink.stb.eq(1),
-			self.sataphy_host.sink.data.eq(SYNC_VAL),
+			self.sataphy_host.sink.data.eq(primitives["SYNC"]),
 			self.sataphy_host.sink.charisk.eq(0b0001)
 		]