From: Connor Abbott <cwabbott0@gmail.com>
Date: Tue, 28 Jan 2020 12:19:25 +0000 (+0100)
Subject: freedreno: Fix CP_COND_REG_EXEC bit positions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=65197a3ac1cf4303e37927ed3faae47e41ee74e6;p=mesa.git

freedreno: Fix CP_COND_REG_EXEC bit positions

Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3600>
---

diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index 78847fbc021..86c4ff0c5f3 100644
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -1473,11 +1473,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 		-->
 
 		<!-- RM6_BINNING -->
-		<bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
+		<bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/>
 		<!-- all others -->
-		<bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
+		<bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/>
 		<!-- RM6_BYPASS -->
-		<bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
+		<bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/>
 
 		<bitfield name="MODE" low="28" high="31" type="compare_mode"/>
 	</reg32>