From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 16:09:30 +0000 (-0800)
Subject: Change literal vars from int to unsigned
X-Git-Tag: yosys-0.9~232^2~28
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=652e414392b8e9e8c7dde74e6f2c2369d8d65a20;p=yosys.git

Change literal vars from int to unsigned
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index abff6d8d9..0414d3db3 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -100,7 +100,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         return wire;
     };
 
-    int l1, l2, l3;
+    unsigned l1, l2, l3;
 
     // Parse inputs
     std::vector<RTLIL::Wire*> inputs;