From: lkcl Date: Sat, 28 May 2022 08:07:12 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~2054 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=652e518bf93664d3de40dcfbf8ee0a149a7cbb85;p=libreriscv.git --- diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index 0ac865971..955955a6b 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -115,9 +115,9 @@ mantissa may be achieved. *IBM may consider it worthwhile to extend these two instructions to v3.1 Prefixed (`pfmvis` and `pfrlsi`). If so it is recommended that -`pfmvis` load a full FP32 immediate and `pfrlsi` supplies the four high -missing exponent bits (8 to 10) and the lower additional -28 mantissa bits (23 to 51) needed to construct a full FP64 immediate.* +`pfmvis` load a full FP32 immediate and `pfrlsi` supplies the three high +missing exponent bits (numbered 8 to 10) and the lower additional +29 mantissa bits (23 to 51) needed to construct a full FP64 immediate.* ## Load BF16 Immediate @@ -179,14 +179,16 @@ DX-Form: Strategically similar to how `oris` is used to construct 32-bit Integers, an additional 16-bits of immediate is inserted into `FRS` to extend its accuracy to -a full FP32. If a prior `fmvis` instruction had been used to +a full FP32 (stored as usual in FP64 Format within the FPR). +If a prior `fmvis` instruction had been used to set the upper 16-bits of an FP32 value, `frlsi` contains the lower 16-bits. The key difference between using `li` and `oris` to construct 32-bit GPR Immediates and `frlsi` is that the `fmvis` will have converted -the `BF16` to FP64 (Double) format. This is taken into consideration -as can be seen in the pseudocode below +the `BF16` immediate to FP64 (Double) format. +This is taken into consideration +as can be seen in the pseudocode below. Pseudocode: