From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Jun 2020 19:15:06 +0000 (+0100)
Subject: remove data_len from SR input record
X-Git-Tag: div_pipeline~668
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=654b4ba10ed097fd609a9f6296bf11cfa43f3a2c;p=soc.git

remove data_len from SR input record
---

diff --git a/src/soc/fu/shift_rot/sr_input_record.py b/src/soc/fu/shift_rot/sr_input_record.py
index 8263410c..57f84dc9 100644
--- a/src/soc/fu/shift_rot/sr_input_record.py
+++ b/src/soc/fu/shift_rot/sr_input_record.py
@@ -26,7 +26,6 @@ class CompSROpSubset(Record):
                   ('output_cr', 1),
                   ('is_32bit', 1),
                   ('is_signed', 1),
-                  ('data_len', 4), # actually used by ALU, in OP_EXTS
                   ('insn', 32),
                   ('byte_reverse', 1),
                   ('sign_extend', 1))
@@ -45,7 +44,6 @@ class CompSROpSubset(Record):
         self.output_cr.reset_less = True
         self.is_32bit.reset_less = True
         self.is_signed.reset_less = True
-        self.data_len.reset_less = True
         self.byte_reverse.reset_less = True
         self.sign_extend.reset_less = True
 
@@ -69,7 +67,6 @@ class CompSROpSubset(Record):
                 self.output_cr,
                 self.is_32bit,
                 self.is_signed,
-                self.data_len,
                 self.byte_reverse,
                 self.sign_extend,
         ]