From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 22 Sep 2020 11:23:25 +0000 (+0100)
Subject: add JTAG bus module
X-Git-Tag: 24jan2021_ls180~357
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=654e2b32ba4c7783fff764d09e5968a723b84cf6;p=soc.git

add JTAG bus module
---

diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py
new file mode 100644
index 00000000..9e28e47b
--- /dev/null
+++ b/src/soc/debug/jtag.py
@@ -0,0 +1,37 @@
+"""JTAG interface
+
+using Staf Verhaegen (Chips4Makers) wishbone TAP
+"""
+
+from nmigen import (Module, Signal, Elaboratable)
+from nmigen.cli import rtlil
+from c4m.nmigen.jtag.tap import IOType
+from soc.debug.dmi import  DMIInterface, DBGCore
+from soc.debug.dmi2jtag import DMITAP
+
+
+class JTAG(DMITAP):
+    iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
+    def __init__(self):
+        super().__init__(ir_width=4)
+        self.ios = [self.add_io(iotype=iotype) for iotype in self.iotypes]
+        self.sr = self.add_shiftreg(ircode=4, length=3)
+
+        # create and connect wishbone 
+        self.wb = self.add_wishbone(ircodes=[5, 6, 7],
+                                   address_width=29, data_width=64)
+
+        # create DMI2JTAG (goes through to dmi_sim())
+        self.dmi = self.add_dmi(ircodes=[8, 9, 10])
+
+    def elaborate(self, platform):
+        return super().elaborate(platform)
+
+
+if __name__ == '__main__':
+    dut = JTAG()
+
+    vl = rtlil.convert(dut)
+    with open("test_jtag.il", "w") as f:
+        f.write(vl)
+