From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 18 Jun 2020 22:31:14 +0000 (-0700)
Subject: Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
X-Git-Tag: div_pipeline~329
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6552ef8cef8fd2b43bbf560332b25825f693b573;hp=475faaa8f469d6c0de73ac9bd98b370664d6f1c8;p=soc.git

Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
---

diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py
index eb4461e0..6265fcbc 100644
--- a/src/soc/fu/div/output_stage.py
+++ b/src/soc/fu/div/output_stage.py
@@ -78,7 +78,7 @@ class DivOutputStage(PipeModBase):
         with m.If(op.is_32bit):
             calc_overflow(self.i.dive_abs_overflow_32, 0x8000_0000)
         with m.Else():
-            calc_overflow(self.i.dive_abs_overflow_32, 0x8000_0000_0000_0000)
+            calc_overflow(self.i.dive_abs_overflow_64, 0x8000_0000_0000_0000)
 
         ##########################
         # main switch for DIV