From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 21:25:56 +0000 (+0100)
Subject: add images
X-Git-Tag: convert-csv-opcode-to-binary~5305
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6559e5b12a251f3bd5b55fe0373fcb5828c960dc;p=libreriscv.git

add images
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index c100bdf41..b2e3c92c0 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -241,7 +241,7 @@
    \item Predication in INT regs as a BIT field (max VL=XLEN)
    \item Minimum VL must be Num Regs - 1 (all regs single LD/ST)
    \item SV may condense sparse Vecs: RVV lets ALU do predication
-   \item NO ZEROING: non-predicated elements are skipped
+   \item Choice to Zero or skip non-predicated elements
   \end{itemize}
 }