From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 27 Nov 2023 13:55:53 +0000 (+0000)
Subject: add gbbd (bmatflip) test case - just the one for now
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=656dbb8bafcfa246b2163760c7c46ff07d6bf2a0;p=openpower-isa.git

add gbbd (bmatflip) test case - just the one for now
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 249a56e7..ae9ea147 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2094,7 +2094,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                        "brh", "brw", "brd",
                        'setvl', 'svindex', 'svremap', 'svstep',
                        'svshape', 'svshape2',
-                       'ternlogi', 'bmask', 'cprop',
+                       'ternlogi', 'bmask', 'cprop', 'gbbd',
                        'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
                        'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
                        "dsld", "dsrd", "maddedus",
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 42d57c6b..c0c1ddca 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -767,6 +767,7 @@ _insns = [
     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
     "fmvis",   # FP load immediate
     "fishmv",  # Float Replace Lower-Half Single, Immediate
+    "gbbd",          # bitmanip - (aka bmatflip)
     "cffpr", "cffpro",
     "mffpr", "mffprs",
     "ctfpr", "ctfprs",
diff --git a/src/openpower/test/bitmanip/bitmanip_cases.py b/src/openpower/test/bitmanip/bitmanip_cases.py
index 494ff0f0..e9f6bb46 100644
--- a/src/openpower/test/bitmanip/bitmanip_cases.py
+++ b/src/openpower/test/bitmanip/bitmanip_cases.py
@@ -5,11 +5,33 @@ from openpower.simulator.program import Program
 from openpower.test.state import ExpectedState
 from nmutil.sim_util import hash_256
 from openpower.decoder.isa.caller import SVP64State
+from openpower.util import log
 import struct
 import itertools
 
+def bmatflip(ra):
+    result = 0
+    for j in range(8):
+        for k in range(8):
+            b = (ra >> (63-k*8-j)) & 1
+            result |= b << (63-j*8-k)
+    return result
+
 
 class BitManipTestCase(TestAccumulatorBase):
+    def case_gbbd(self):
+        lst = ["gbbd 0, 1"]
+        lst = list(SVP64Asm(lst, bigendian))
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x9231_5897_2083_ffff
+        e = ExpectedState(pc=4)
+        e.intregs[0] = bmatflip(initial_regs[1])
+        e.intregs[1] = initial_regs[1]
+        log("case_gbbd", bin(initial_regs[1]), bin(e.intregs[0]))
+        log("hex", hex(initial_regs[1]), hex(e.intregs[0]))
+
+        self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
     def do_case_ternlogi(self, rc, rt, ra, rb, imm):
         rc_dot = "." if rc else ""
         lst = [f"ternlogi{rc_dot} 3, 4, 5, {imm}"]