From: lkcl Date: Mon, 21 Dec 2020 18:12:41 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~1076 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6572ea62d59dadb60ec67fcec5bd040640b8be61;p=libreriscv.git --- diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn index c352ae603..b8e6fcaec 100644 --- a/openpower/sv/svp_rewrite/svp64.mdwn +++ b/openpower/sv/svp_rewrite/svp64.mdwn @@ -45,7 +45,7 @@ simply neither read nor written. This includes when `scalar identity behaviour` An interesting side-effect of this decision is that the OE flag is now free for other uses when SV Prefixing is used. -# Additional instructions: v3.0B/v3.1B overrides +# Additional instructions: v3.0B/v3.1B alternatives SV is primarily designed for use as an efficient hybrid 3D GPU / VPU / CPU ISA. @@ -55,6 +55,8 @@ This leaves several Major Opcodes free for use by SV to fit alternative instruct Note however that svp64 is stand-alone and is in no way critically dependent on the existence or provision of 3D GPU or VPU instructions. These should be considered extensions, and their discussion and specification is out of scope for this document. +Note, again: this is *only* under svp64 prefixing. Standard v3.0B / v3.1B is *not* altered by svp64. + # Register Naming and size SV Registers are simply the INT, FP and CR register files extended