From: lkcl <lkcl@web>
Date: Wed, 20 Jul 2022 15:29:17 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1156
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=657457b722900c8a8d3644159c160f66ac02f372;p=libreriscv.git

---

diff --git a/openpower.mdwn b/openpower.mdwn
index 69f7ee449..38e10eb2d 100644
--- a/openpower.mdwn
+++ b/openpower.mdwn
@@ -80,14 +80,6 @@ Thus it is completely unnecessary to add any vector opcodes - at all -
 saving hugely on both hardware and compiler development time when
 the concept is dropped on top of a pre-existing ISA.
 
-## Condition Registers
-
-Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
-
-## Carry
-
-SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Most sensible location to use is the CRs
-
 # Integer Overflow / Saturate
 
 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.